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Disable AVX-512VL insns for scalar mode operands on -march=knl. 

gcc/
	* config/i386/i386.md (define_attr "isa"): Addd avx512vl and
	noavx512vl.
	(define_attr "enabled"): Handle avx521vl and noavx512vl.
	* config/i386/sse.md (define_insn "vec_dupv2df<mask_name>"): Split
	AVX-512 alternative out of SSE.
	(define_insn "*vec_concatv2df"): Ditto.

From-SVN: r226612
This commit is contained in:
Kirill Yukhin 2015-08-05 08:01:19 +00:00 committed by Kirill Yukhin
parent 0ea424263f
commit f4904740e7
3 changed files with 32 additions and 14 deletions
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9
gcc/ChangeLog
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@ -1,3 +1,12 @@
2015-08-05 Kirill Yukhin <kirill.yukhin@intel.com>
* config/i386/i386.md (define_attr "isa"): Addd avx512vl and
noavx512vl.
(define_attr "enabled"): Handle avx521vl and noavx512vl.
* config/i386/sse.md (define_insn "vec_dupv2df<mask_name>"): Split
AVX-512 alternative out of SSE.
(define_insn "*vec_concatv2df"): Ditto.
2015-08-05 Kirill Yukhin <kirill.yukhin@intel.com> 2015-08-05 Kirill Yukhin <kirill.yukhin@intel.com>
* config/i386/i386.c (bdesc_args): Rename CODE_FOR_sse4_1_ptest into * config/i386/i386.c (bdesc_args): Rename CODE_FOR_sse4_1_ptest into

5
gcc/config/i386/i386.md
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@ -784,7 +784,8 @@
(define_attr "isa" "base,x64,x64_sse4,x64_sse4_noavx,x64_avx,nox64, (define_attr "isa" "base,x64,x64_sse4,x64_sse4_noavx,x64_avx,nox64,
sse2,sse2_noavx,sse3,sse4,sse4_noavx,avx,noavx, sse2,sse2_noavx,sse3,sse4,sse4_noavx,avx,noavx,
avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f, avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f,
fma_avx512f,avx512bw,noavx512bw,avx512dq,noavx512dq" fma_avx512f,avx512bw,noavx512bw,avx512dq,noavx512dq,
avx512vl,noavx512vl"
(const_string "base")) (const_string "base"))
(define_attr "enabled" "" (define_attr "enabled" ""
@ -819,6 +820,8 @@
(eq_attr "isa" "noavx512bw") (symbol_ref "!TARGET_AVX512BW") (eq_attr "isa" "noavx512bw") (symbol_ref "!TARGET_AVX512BW")
(eq_attr "isa" "avx512dq") (symbol_ref "TARGET_AVX512DQ") (eq_attr "isa" "avx512dq") (symbol_ref "TARGET_AVX512DQ")
(eq_attr "isa" "noavx512dq") (symbol_ref "!TARGET_AVX512DQ") (eq_attr "isa" "noavx512dq") (symbol_ref "!TARGET_AVX512DQ")
(eq_attr "isa" "avx512vl") (symbol_ref "TARGET_AVX512VL")
(eq_attr "isa" "noavx512vl") (symbol_ref "!TARGET_AVX512VL")
] ]
(const_int 1))) (const_int 1)))

32
gcc/config/i386/sse.md
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@ -8648,44 +8648,50 @@
(set_attr "mode" "DF,DF,V1DF,V1DF,V1DF,V2DF,V1DF,V1DF,V1DF")]) (set_attr "mode" "DF,DF,V1DF,V1DF,V1DF,V2DF,V1DF,V1DF,V1DF")])
(define_insn "vec_dupv2df<mask_name>" (define_insn "vec_dupv2df<mask_name>"
[(set (match_operand:V2DF 0 "register_operand" "=x,v") [(set (match_operand:V2DF 0 "register_operand" "=x,x,v")
(vec_duplicate:V2DF (vec_duplicate:V2DF
(match_operand:DF 1 "nonimmediate_operand" " 0,vm")))] (match_operand:DF 1 "nonimmediate_operand" " 0,xm,vm")))]
"TARGET_SSE2 && <mask_avx512vl_condition>" "TARGET_SSE2 && <mask_avx512vl_condition>"
"@ "@
unpcklpd\t%0, %0 unpcklpd\t%0, %0
%vmovddup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}" %vmovddup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}
[(set_attr "isa" "noavx,sse3") vmovddup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "isa" "noavx,sse3,avx512vl")
(set_attr "type" "sselog1") (set_attr "type" "sselog1")
(set_attr "prefix" "orig,maybe_vex") (set_attr "prefix" "orig,maybe_vex,evex")
(set_attr "mode" "V2DF,DF")]) (set_attr "mode" "V2DF,DF,DF")])
(define_insn "*vec_concatv2df" (define_insn "*vec_concatv2df"
[(set (match_operand:V2DF 0 "register_operand" "=x,v,v,x,x,v,x,x") [(set (match_operand:V2DF 0 "register_operand" "=x,x,v,x,v,x,x,v,x,x")
(vec_concat:V2DF (vec_concat:V2DF
(match_operand:DF 1 "nonimmediate_operand" " 0,v,m,0,x,m,0,0") (match_operand:DF 1 "nonimmediate_operand" " 0,x,v,m,m,0,x,m,0,0")
(match_operand:DF 2 "vector_move_operand" " x,v,1,m,m,C,x,m")))] (match_operand:DF 2 "vector_move_operand" " x,x,v,1,1,m,m,C,x,m")))]
"TARGET_SSE "TARGET_SSE
&& (!(MEM_P (operands[1]) && MEM_P (operands[2])) && (!(MEM_P (operands[1]) && MEM_P (operands[2]))
|| (TARGET_SSE3 && rtx_equal_p (operands[1], operands[2])))" || (TARGET_SSE3 && rtx_equal_p (operands[1], operands[2])))"
"@ "@
unpcklpd\t{%2, %0|%0, %2} unpcklpd\t{%2, %0|%0, %2}
vunpcklpd\t{%2, %1, %0|%0, %1, %2} vunpcklpd\t{%2, %1, %0|%0, %1, %2}
vunpcklpd\t{%2, %1, %0|%0, %1, %2}
%vmovddup\t{%1, %0|%0, %1} %vmovddup\t{%1, %0|%0, %1}
vmovddup\t{%1, %0|%0, %1}
movhpd\t{%2, %0|%0, %2} movhpd\t{%2, %0|%0, %2}
vmovhpd\t{%2, %1, %0|%0, %1, %2} vmovhpd\t{%2, %1, %0|%0, %1, %2}
%vmovsd\t{%1, %0|%0, %1} %vmovsd\t{%1, %0|%0, %1}
movlhps\t{%2, %0|%0, %2} movlhps\t{%2, %0|%0, %2}
movhps\t{%2, %0|%0, %2}" movhps\t{%2, %0|%0, %2}"
[(set_attr "isa" "sse2_noavx,avx,sse3,sse2_noavx,avx,sse2,noavx,noavx") [(set_attr "isa" "sse2_noavx,avx,avx512vl,sse3,avx512vl,sse2_noavx,avx,sse2,noavx,noavx")
(set (attr "type") (set (attr "type")
(if_then_else (if_then_else
(eq_attr "alternative" "0,1,2") (eq_attr "alternative" "0,1,2")
(const_string "sselog") (const_string "sselog")
(const_string "ssemov"))) (const_string "ssemov")))
(set_attr "prefix_data16" "*,*,*,1,*,*,*,*") (set (attr "prefix_data16")
(set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex,orig,orig") (if_then_else (eq_attr "alternative" "5")
(set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,DF,V4SF,V2SF")]) (const_string "1")
(const_string "*")))
(set_attr "prefix" "orig,vex,evex,maybe_vex,evex,orig,vex,maybe_vex,orig,orig")
(set_attr "mode" "V2DF,V2DF,V2DF, DF, DF, V1DF,V1DF,DF,V4SF,V2SF")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; ;;