mirror of git://gcc.gnu.org/git/gcc.git
i386.h (SSE_VEC_FLOAT_MODE_P): Remove.
* config/i386/i386.h (SSE_VEC_FLOAT_MODE_P): Remove. (AVX_FLOAT_MODE_P): Ditto. (AVX128_VEC_FLOAT_MODE_P): Ditto. (AVX256_VEC_FLOAT_MODE_P): Ditto. (AVX_VEC_FLOAT_MODE_P): Ditto. * config/i386/i386.md (UNSPEC_MASKLOAD): Remove. (UNSPEC_MASKSTORE): Ditto. * config/i386/sse.md (<sse>_movmsk<ssemodesuffix><avxmodesuffix>): Merge from <sse>_movmsk<ssemodesuffix> and avx_movmsk<ssemodesuffix>256. Use VF mode iterator. (*sse2_maskmovdqu): Merge with *sse2_maskmovdqu_rex64. Use P mode iterator. (avx_maskload<ssemodesuffix><avxmodesuffix>): New expander. (avx_maskstore<ssemodesuffix><avxmodesuffix>): Ditto. (*avx_maskmov<ssemodesuffix><avxmodesuffix>): New insn. testsuite/ChangeLog: * gcc.target/i386/sse2-maskmovdqu.c: New test. * gcc.target/i386/avx-vmaskmovdqu.c: Ditto. From-SVN: r172669
This commit is contained in:
Uros Bizjak
parent
d77c2e5b86
commit
f60c25544c
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@ -1,3 +1,21 @@
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2011-04-18 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.h (SSE_VEC_FLOAT_MODE_P): Remove.
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(AVX_FLOAT_MODE_P): Ditto.
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(AVX128_VEC_FLOAT_MODE_P): Ditto.
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(AVX256_VEC_FLOAT_MODE_P): Ditto.
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(AVX_VEC_FLOAT_MODE_P): Ditto.
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* config/i386/i386.md (UNSPEC_MASKLOAD): Remove.
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(UNSPEC_MASKSTORE): Ditto.
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* config/i386/sse.md (<sse>_movmsk<ssemodesuffix><avxmodesuffix>):
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Merge from <sse>_movmsk<ssemodesuffix> and
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avx_movmsk<ssemodesuffix>256. Use VF mode iterator.
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(*sse2_maskmovdqu): Merge with *sse2_maskmovdqu_rex64. Use P mode
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iterator.
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(avx_maskload<ssemodesuffix><avxmodesuffix>): New expander.
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(avx_maskstore<ssemodesuffix><avxmodesuffix>): Ditto.
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(*avx_maskmov<ssemodesuffix><avxmodesuffix>): New insn.
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2011-04-18 Jan Hubicka <jh@suse.cz>
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* ipa-inline.c (inline_small_functions): Fix pasto in previous patch.
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@ -10,8 +28,7 @@
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(inline_small_functions): Move program size estimates here;
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actually process whole queue even when unit growth has been
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met. (to properly compute inline_failed reasons and for the
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case unit size decrease.) Revisit comments on recursive
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inlining.
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case unit size decrease.) Revisit comments on recursive inlining.
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(ipa_inline): Remove unit summary code; first inline hot calls
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of functions called once, cold calls next.
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(order, nnodes): Remove unused variables.
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@ -164,17 +181,16 @@
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want_inline_small_function_p.
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(cgraph_decide_recursive_inlining): Rename to...
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(recursive_inlining): Use can_inline_edge_p and
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want_inline_self_recursive_call_p; simplify and
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remove no longer valid FIXME.
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want_inline_self_recursive_call_p; simplify and remove no longer
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valid FIXME.
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(cgraph_set_inline_failed): Remove.
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(add_new_edges_to_heap): Use can_inline_edge_p and
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want_inline_small_function_p.
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(cgraph_decide_inlining_of_small_functions): Rename to ...
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(inline_small_functions): ... this one; cleanup; use
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can/want predicates; cleanup debug ouput; work edges
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till fibheap is exhausted and do not stop once unit
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growth is reached; remove later loop processing remaining
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edges.
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can/want predicates; cleanup debug ouput; work edges till fibheap
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is exhausted and do not stop once unit growth is reached; remove
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later loop processing remaining edges.
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(cgraph_flatten): Rename to ...
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(flatten_function): ... this one; use can_inline_edge_p
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and can_early_inline_edge_p predicates.
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@ -183,8 +199,7 @@
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inlining functions called once; simplify the pass.
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(cgraph_perform_always_inlining): Rename to ...
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(inline_always_inline_functions): ... this one; use
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DECL_DISREGARD_INLINE_LIMITS; use can_inline_edge_p
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predicate
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DECL_DISREGARD_INLINE_LIMITS; use can_inline_edge_p predicate.
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(cgraph_decide_inlining_incrementally): Rename to ...
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(early_inline_small_functions): ... this one; simplify
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using new predicates; cleanup; make dumps prettier.
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@ -290,8 +305,8 @@
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(initialize_inline_failed): Move here from cgraph.c.
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* tree-sra.c: Include ipa-inline.h.
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(ipa_sra_preliminary_function_checks): Update.
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* Makefile.in: (cgraph.o, cgraphbuild.o): Add dependency on
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ipa-inline.h
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* Makefile.in (cgraph.o, cgraphbuild.o): Add dependency on
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ipa-inline.h.
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2011-04-16 Uros Bizjak <ubizjak@gmail.com>
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@ -618,7 +633,7 @@
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Eric Weddington <eric.weddington@atmel.com>
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Georg-Johann Lay <avr@gjlay.de>
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* config/avr/avr.c: ("insn-codes.h", "optabs.h", "langhooks.h"):
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* config/avr/avr.c ("insn-codes.h", "optabs.h", "langhooks.h"):
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New Includes
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(avr_init_builtins, avr_expand_builtin,
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avr_expand_delay_cycles, avr_expand_unop_builtin,
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@ -3256,7 +3271,7 @@
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2010-08-13 Vladimir Makarov <vmakarov@redhat.com>
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* ira-build.c: (ira_create_object): Remove initialization of
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* ira-build.c (ira_create_object): Remove initialization of
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OBJECT_PROFITABLE_HARD_REGS. Initialize OBJECT_ADD_DATA.
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(ira_create_allocno): Remove initialization of
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ALLOCNO_MEM_OPTIMIZED_DEST, ALLOCNO_MEM_OPTIMIZED_DEST_P,
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@ -3382,7 +3397,7 @@
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ira_object_conflict_iter_cond.
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(FOR_EACH_OBJECT_CONFLICT): Don't use ira_object_conflict_iter_next.
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* ira-live.c: (process_single_reg_class_operands): Call
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* ira-live.c (process_single_reg_class_operands): Call
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ira_init_register_move_cost_if_necessary. Use
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ira_register_move_cost instead of ira_get_register_move_cost.
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@ -6172,7 +6187,7 @@
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2011-03-14 Andreas Tobler <andreast@fgznet.ch>
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* config/rs6000/freebsd.h: (RELOCATABLE_NEEDS_FIXUP): Define in
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* config/rs6000/freebsd.h (RELOCATABLE_NEEDS_FIXUP): Define in
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terms of target_flags_explicit. Adjust copyright year.
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* config.gcc: Add FreeBSD PowerPC soft-float libgcc bits.
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@ -10408,7 +10423,7 @@
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2011-01-07 Jan Hubicka <jh@suse.cz>
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* doc/invoke.texi: (-flto, -fuse-linker-plugin): Update defaults
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* doc/invoke.texi (-flto, -fuse-linker-plugin): Update defaults
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and no longer claim that gold is required for linker plugin.
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* configure: Regenerate.
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* gcc.c (PLUGIN_COND): New macro.
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@ -1328,22 +1328,6 @@ enum reg_class
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#define SSE_FLOAT_MODE_P(MODE) \
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((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
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#define SSE_VEC_FLOAT_MODE_P(MODE) \
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((TARGET_SSE && (MODE) == V4SFmode) || (TARGET_SSE2 && (MODE) == V2DFmode))
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#define AVX_FLOAT_MODE_P(MODE) \
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(TARGET_AVX && ((MODE) == SFmode || (MODE) == DFmode))
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#define AVX128_VEC_FLOAT_MODE_P(MODE) \
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(TARGET_AVX && ((MODE) == V4SFmode || (MODE) == V2DFmode))
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#define AVX256_VEC_FLOAT_MODE_P(MODE) \
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(TARGET_AVX && ((MODE) == V8SFmode || (MODE) == V4DFmode))
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#define AVX_VEC_FLOAT_MODE_P(MODE) \
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(TARGET_AVX && ((MODE) == V4SFmode || (MODE) == V2DFmode \
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|| (MODE) == V8SFmode || (MODE) == V4DFmode))
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#define FMA4_VEC_FLOAT_MODE_P(MODE) \
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(TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \
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|| (MODE) == V8SFmode || (MODE) == V4DFmode))
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@ -224,8 +224,6 @@
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UNSPEC_VPERMIL
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UNSPEC_VPERMIL2
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UNSPEC_VPERMIL2F128
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UNSPEC_MASKLOAD
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UNSPEC_MASKSTORE
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UNSPEC_CAST
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UNSPEC_VTESTP
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UNSPEC_VCVTPH2PS
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@ -6893,23 +6893,12 @@
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(set_attr "prefix" "orig,vex")
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(set_attr "mode" "TI")])
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(define_insn "avx_movmsk<ssemodesuffix>256"
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(define_insn "<sse>_movmsk<ssemodesuffix><avxmodesuffix>"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI
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[(match_operand:AVX256MODEF2P 1 "register_operand" "x")]
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[(match_operand:VF 1 "register_operand" "x")]
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UNSPEC_MOVMSK))]
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"AVX256_VEC_FLOAT_MODE_P (<MODE>mode)"
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"vmovmsk<ssemodesuffix>\t{%1, %0|%0, %1}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "vex")
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(set_attr "mode" "<MODE>")])
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(define_insn "<sse>_movmsk<ssemodesuffix>"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI
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[(match_operand:SSEMODEF2P 1 "register_operand" "x")]
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UNSPEC_MOVMSK))]
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"SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
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""
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"%vmovmsk<ssemodesuffix>\t{%1, %0|%0, %1}"
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[(set_attr "type" "ssemov")
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(set_attr "prefix" "maybe_vex")
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@ -6935,35 +6924,18 @@
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"TARGET_SSE2")
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(define_insn "*sse2_maskmovdqu"
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[(set (mem:V16QI (match_operand:SI 0 "register_operand" "D"))
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[(set (mem:V16QI (match_operand:P 0 "register_operand" "D"))
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(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
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(match_operand:V16QI 2 "register_operand" "x")
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(mem:V16QI (match_dup 0))]
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UNSPEC_MASKMOV))]
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"TARGET_SSE2 && !TARGET_64BIT"
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;; @@@ check ordering of operands in intel/nonintel syntax
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"%vmaskmovdqu\t{%2, %1|%1, %2}"
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[(set_attr "type" "ssemov")
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(set_attr "prefix_data16" "1")
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;; The implicit %rdi operand confuses default length_vex computation.
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(set_attr "length_vex" "3")
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "TI")])
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(define_insn "*sse2_maskmovdqu_rex64"
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[(set (mem:V16QI (match_operand:DI 0 "register_operand" "D"))
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(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
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(match_operand:V16QI 2 "register_operand" "x")
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(mem:V16QI (match_dup 0))]
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UNSPEC_MASKMOV))]
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"TARGET_SSE2 && TARGET_64BIT"
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;; @@@ check ordering of operands in intel/nonintel syntax
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"TARGET_SSE2"
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"%vmaskmovdqu\t{%2, %1|%1, %2}"
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[(set_attr "type" "ssemov")
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(set_attr "prefix_data16" "1")
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;; The implicit %rdi operand confuses default length_vex computation.
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(set (attr "length_vex")
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(symbol_ref ("REGNO (operands[2]) >= FIRST_REX_SSE_REG ? 3 + 1 : 2 + 1")))
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(symbol_ref ("3 + REX_SSE_REGNO_P (REGNO (operands[2]))")))
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "TI")])
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@ -10349,28 +10321,33 @@
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(set_attr "prefix" "vex")
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(set_attr "mode" "V8SF")])
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(define_insn "avx_maskload<ssemodesuffix><avxmodesuffix>"
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[(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
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(unspec:AVXMODEF2P
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[(match_operand:AVXMODEF2P 1 "memory_operand" "m")
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(match_operand:<avxpermvecmode> 2 "register_operand" "x")
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(define_expand "avx_maskload<ssemodesuffix><avxmodesuffix>"
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[(set (match_operand:VF 0 "register_operand" "")
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(unspec:VF
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[(match_operand:<avxpermvecmode> 2 "register_operand" "")
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(match_operand:VF 1 "memory_operand" "")
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(match_dup 0)]
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UNSPEC_MASKLOAD))]
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"TARGET_AVX"
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"vmaskmov<ssemodesuffix>\t{%1, %2, %0|%0, %2, %1}"
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[(set_attr "type" "sselog1")
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(set_attr "prefix_extra" "1")
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(set_attr "prefix" "vex")
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(set_attr "mode" "<MODE>")])
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UNSPEC_MASKMOV))]
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"TARGET_AVX")
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(define_insn "avx_maskstore<ssemodesuffix><avxmodesuffix>"
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[(set (match_operand:AVXMODEF2P 0 "memory_operand" "=m")
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(unspec:AVXMODEF2P
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[(match_operand:<avxpermvecmode> 1 "register_operand" "x")
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(match_operand:AVXMODEF2P 2 "register_operand" "x")
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(define_expand "avx_maskstore<ssemodesuffix><avxmodesuffix>"
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[(set (match_operand:VF 0 "memory_operand" "")
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(unspec:VF
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[(match_operand:<avxpermvecmode> 1 "register_operand" "")
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(match_operand:VF 2 "register_operand" "")
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(match_dup 0)]
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UNSPEC_MASKSTORE))]
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"TARGET_AVX"
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UNSPEC_MASKMOV))]
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"TARGET_AVX")
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(define_insn "*avx_maskmov<ssemodesuffix><avxmodesuffix>"
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[(set (match_operand:VF 0 "nonimmediate_operand" "=x,m")
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(unspec:VF
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[(match_operand:<avxpermvecmode> 1 "register_operand" "x,x")
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(match_operand:VF 2 "nonimmediate_operand" "m,x")
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(match_dup 0)]
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UNSPEC_MASKMOV))]
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"TARGET_AVX
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&& (REG_P (operands[0]) == MEM_P (operands[2]))"
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"vmaskmov<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "type" "sselog1")
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(set_attr "prefix_extra" "1")
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@ -1,3 +1,8 @@
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2011-04-18 Uros Bizjak <ubizjak@gmail.com>
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* gcc.target/i386/sse2-maskmovdqu.c: New test.
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* gcc.target/i386/avx-vmaskmovdqu.c: Ditto.
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2011-04-18 Tobias Burnus <burnus@net-b.de>
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PR fortran/18918
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@ -0,0 +1,8 @@
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/* { dg-do run } */
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/* { dg-require-effective-target avx } */
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/* { dg-options "-O2 -mavx" } */
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#define CHECK_H "avx-check.h"
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#define TEST avx_test
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#include "sse2-maskmovdqu.c"
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@ -0,0 +1,44 @@
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/* { dg-do run } */
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/* { dg-require-effective-target sse2 } */
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/* { dg-options "-O2 -msse2" } */
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#ifndef CHECK_H
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#define CHECK_H "sse2-check.h"
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#endif
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#ifndef TEST
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#define TEST sse2_test
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#endif
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#include CHECK_H
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#include <emmintrin.h>
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#ifndef MASK
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#define MASK 0x7986
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#endif
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#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 7)
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void static
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TEST (void)
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{
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__m128i src, mask;
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char s[16] = { 1,-2,3,-4,5,-6,7,-8,9,-10,11,-12,13,-14,15,-16 };
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char m[16];
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char u[20] = { 0 };
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int i;
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for (i = 0; i < 16; i++)
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m[i] = mask_v (i);
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src = _mm_loadu_si128 ((__m128i *)s);
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mask = _mm_loadu_si128 ((__m128i *)m);
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_mm_maskmoveu_si128 (src, mask, u+3);
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for (i = 0; i < 16; i++)
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if (u[i+3] != (m[i] ? s[i] : 0))
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abort ();
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}
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Loading…
Reference in New Issue