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This commit is contained in:
Michael Meissner 2025-10-17 04:23:33 -04:00
parent 3967387d94
commit f69be51e46
2 changed files with 5 additions and 16 deletions
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13
gcc/ChangeLog.float
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@ -1,15 +1,4 @@
==================== Branch work222-float, patch #337 ====================
Fix 16-bit floating point ordering.
2025-10-17 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/ffloat16.md (vec_unpacks_hi_v8hf): Fix ordering issue.
(vec_unpacks_lo_v8hf): Likewise.
(vec_unpacks_hi_v8bf): Likewise.
(vec_unpacks_lo_v8bf): Likewise.
==================== Branch work222-float, patch #337 was reverted ====================
==================== Branch work222-float, patch #336 ====================

8
gcc/config/rs6000/float16.md
View File

@ -1013,7 +1013,7 @@
{
rtx reg = gen_reg_rtx (V8HFmode);
rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);
rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);
emit_insn (gen_xvcvhpsp_v8hf (operands[0], reg));
DONE;
})
@ -1025,7 +1025,7 @@
{
rtx reg = gen_reg_rtx (V8HFmode);
rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);
rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);
emit_insn (gen_xvcvhpsp_v8hf (operands[0], reg));
DONE;
})
@ -1047,7 +1047,7 @@
{
rtx reg = gen_reg_rtx (V8BFmode);
rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);
rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);
emit_insn (gen_xvcvbf16spn_v8bf (operands[0], reg));
DONE;
})
@ -1059,7 +1059,7 @@
{
rtx reg = gen_reg_rtx (V8BFmode);
rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);
rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);
emit_insn (gen_xvcvbf16spn_v8bf (operands[0], reg));
DONE;
})