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From-SVN: r248988
This commit is contained in:
Segher Boessenkool 2017-06-07 17:35:40 +02:00
parent be9596fe8f
commit fa1ae56a2f
4 changed files with 0 additions and 1212 deletions
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45
gcc/config/rs6000/e500.h
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/* Enable E500 support.
Copyright (C) 2003-2017 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#undef TARGET_SPE_ABI
#undef TARGET_SPE
#undef TARGET_FPRS
#undef TARGET_E500_SINGLE
#undef TARGET_E500_DOUBLE
#undef CHECK_E500_OPTIONS
#define TARGET_SPE_ABI rs6000_spe_abi
#define TARGET_SPE rs6000_spe
#define TARGET_FPRS (rs6000_float_gprs == 0)
#define TARGET_E500_SINGLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 1)
#define TARGET_E500_DOUBLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 2)
#define CHECK_E500_OPTIONS \
do { \
if (TARGET_SPE || TARGET_SPE_ABI \
|| TARGET_E500_SINGLE || TARGET_E500_DOUBLE) \
{ \
if (TARGET_ALTIVEC) \
error ("AltiVec and SPE instructions cannot coexist"); \
if (TARGET_VSX) \
error ("VSX and SPE instructions cannot coexist"); \
if (TARGET_64BIT) \
error ("64-bit SPE not supported"); \
if (TARGET_HARD_FLOAT && TARGET_FPRS) \
error ("E500 and FPRs not supported"); \
} \
} while (0)

32
gcc/config/rs6000/linuxspe.h
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/* Definitions of target machine for GNU compiler,
for PowerPC e500 machines running GNU/Linux.
Copyright (C) 2003-2017 Free Software Foundation, Inc.
Contributed by Aldy Hernandez (aldy@quesejoda.com).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Override rs6000.h and sysv4.h definition. */
#if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN)
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_STRICT_ALIGN | MASK_LITTLE_ENDIAN)
#else
#undef TARGET_DEFAULT
#define TARGET_DEFAULT MASK_STRICT_ALIGN
#endif
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-mppc -mspe -me500"

1107
gcc/config/rs6000/spe.h
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28
gcc/config/rs6000/spe.md
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;; e500 SPE description
;; Copyright (C) 2002-2017 Free Software Foundation, Inc.
;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
;; License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; Modes using a 64-bit register.
(define_mode_iterator SPE64 [DF V4HI V2SF V1DI V2SI])
;; Likewise, but allow TFmode (two registers) as well.
(define_mode_iterator SPE64TF [DF V4HI V2SF V1DI V2SI TF])
;; DImode and TImode.
(define_mode_iterator DITI [DI TI])