mirror of git://gcc.gnu.org/git/gcc.git
Some patterns for moving one bit around by BST + BLD.
* config/avr/avr.md (any_extract, any_shiftrt): New code iterators. (*insv.extract, *insv.shiftrt, *insv.not-bit.0, *insv.not-bit.7) (*insv.xor-extract, *insv.xor1-bit.0): New insns. (adjust_len) [insv_notbit, insv_notbit_0, insv_notbit_7]: New values for insn attribute. * config/avr/avr.c (avr_out_insert_notbit): New function. (avr_adjust_insn_length): Handle ADJUST_LEN_INSV_NOTBIT, ADJUST_LEN_INSV_NOTBIT_0/_7. * config/avr/avr-protos.h (avr_out_insert_notbit): New proto. From-SVN: r238587
This commit is contained in:
Georg-Johann Lay
Georg-Johann Lay
parent
b24d942079
commit
fa62698775
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@ -1,3 +1,15 @@
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2016-07-21 Georg-Johann Lay <avr@gjlay.de>
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* config/avr/avr.md (any_extract, any_shiftrt): New code iterators.
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(*insv.extract, *insv.shiftrt, *insv.not-bit.0, *insv.not-bit.7)
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(*insv.xor-extract, *insv.xor1-bit.0): New insns.
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(adjust_len) [insv_notbit, insv_notbit_0, insv_notbit_7]: New
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values for insn attribute.
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* config/avr/avr.c (avr_out_insert_notbit): New function.
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(avr_adjust_insn_length): Handle ADJUST_LEN_INSV_NOTBIT,
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ADJUST_LEN_INSV_NOTBIT_0/_7.
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* config/avr/avr-protos.h (avr_out_insert_notbit): New proto.
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2016-07-21 Bin Cheng <bin.cheng@arm.com>
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* tree-chrec.c (convert_affine_scev): New parameter. Pass new arg.
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@ -58,6 +58,7 @@ extern const char *avr_out_compare64 (rtx_insn *, rtx*, int*);
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extern const char *ret_cond_branch (rtx x, int len, int reverse);
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extern const char *avr_out_movpsi (rtx_insn *, rtx*, int*);
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extern const char *avr_out_sign_extend (rtx_insn *, rtx*, int*);
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extern const char *avr_out_insert_notbit (rtx_insn *, rtx*, rtx, int*);
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extern const char *ashlqi3_out (rtx_insn *insn, rtx operands[], int *len);
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extern const char *ashlhi3_out (rtx_insn *insn, rtx operands[], int *len);
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@ -7973,6 +7973,76 @@ avr_out_addto_sp (rtx *op, int *plen)
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}
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/* Output instructions to insert an inverted bit into OPERANDS[0]:
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$0.$1 = ~$2.$3 if XBITNO = NULL
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$0.$1 = ~$2.XBITNO if XBITNO != NULL.
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If PLEN = NULL then output the respective instruction sequence which
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is a combination of BST / BLD and some instruction(s) to invert the bit.
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If PLEN != NULL then store the length of the sequence (in words) in *PLEN.
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Return "". */
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const char*
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avr_out_insert_notbit (rtx_insn *insn, rtx operands[], rtx xbitno, int *plen)
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{
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rtx op[4] = { operands[0], operands[1], operands[2],
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xbitno == NULL_RTX ? operands [3] : xbitno };
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if (INTVAL (op[1]) == 7
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&& test_hard_reg_class (LD_REGS, op[0]))
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{
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/* If the inserted bit number is 7 and we have a d-reg, then invert
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the bit after the insertion by means of SUBI *,0x80. */
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if (INTVAL (op[3]) == 7
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&& REGNO (op[0]) == REGNO (op[2]))
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{
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avr_asm_len ("subi %0,0x80", op, plen, -1);
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}
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else
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{
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avr_asm_len ("bst %2,%3" CR_TAB
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"bld %0,%1" CR_TAB
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"subi %0,0x80", op, plen, -3);
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}
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}
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else if (test_hard_reg_class (LD_REGS, op[0])
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&& (INTVAL (op[1]) != INTVAL (op[3])
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|| !reg_overlap_mentioned_p (op[0], op[2])))
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{
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/* If the destination bit is in a d-reg we can jump depending
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on the source bit and use ANDI / ORI. This just applies if we
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have not an early-clobber situation with the bit. */
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avr_asm_len ("andi %0,~(1<<%1)" CR_TAB
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"sbrs %2,%3" CR_TAB
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"ori %0,1<<%1", op, plen, -3);
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}
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else
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{
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/* Otherwise, invert the bit by means of COM before we store it with
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BST and then undo the COM if needed. */
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avr_asm_len ("com %2" CR_TAB
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"bst %2,%3", op, plen, -2);
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if (!reg_unused_after (insn, op[2])
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// A simple 'reg_unused_after' is not enough because that function
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// assumes that the destination register is overwritten completely
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// and hence is in order for our purpose. This is not the case
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// with BLD which just changes one bit of the destination.
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|| reg_overlap_mentioned_p (op[0], op[2]))
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{
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/* Undo the COM from above. */
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avr_asm_len ("com %2", op, plen, 1);
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}
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avr_asm_len ("bld %0,%1", op, plen, 1);
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}
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return "";
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}
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/* Outputs instructions needed for fixed point type conversion.
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This includes converting between any fixed point type, as well
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as converting to any integer type. Conversion between integer
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@ -8810,6 +8880,16 @@ avr_adjust_insn_length (rtx_insn *insn, int len)
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case ADJUST_LEN_INSERT_BITS: avr_out_insert_bits (op, &len); break;
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case ADJUST_LEN_INSV_NOTBIT:
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avr_out_insert_notbit (insn, op, NULL_RTX, &len);
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break;
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case ADJUST_LEN_INSV_NOTBIT_0:
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avr_out_insert_notbit (insn, op, const0_rtx, &len);
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break;
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case ADJUST_LEN_INSV_NOTBIT_7:
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avr_out_insert_notbit (insn, op, GEN_INT (7), &len);
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break;
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default:
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gcc_unreachable();
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}
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@ -156,7 +156,7 @@
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ashlhi, ashrhi, lshrhi,
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ashlsi, ashrsi, lshrsi,
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ashlpsi, ashrpsi, lshrpsi,
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insert_bits,
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insert_bits, insv_notbit, insv_notbit_0, insv_notbit_7,
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no"
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(const_string "no"))
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@ -264,6 +264,8 @@
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;; Define two incarnations so that we can build the cross product.
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(define_code_iterator any_extend [sign_extend zero_extend])
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(define_code_iterator any_extend2 [sign_extend zero_extend])
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(define_code_iterator any_extract [sign_extract zero_extract])
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(define_code_iterator any_shiftrt [lshiftrt ashiftrt])
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(define_code_iterator xior [xor ior])
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(define_code_iterator eqne [eq ne])
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@ -6485,6 +6487,11 @@
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(match_operand:QI 3 "nonmemory_operand" ""))]
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"optimize")
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;; Some more patterns to support moving around one bit which can be accomplished
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;; by BST + BLD in most situations. Unfortunately, there is no canonical
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;; representation, and we just implement some more cases that are not too
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;; complicated.
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;; Insert bit $2.0 into $0.$1
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(define_insn "*insv.reg"
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[(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r,d,d,l,l")
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@ -6501,6 +6508,103 @@
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[(set_attr "length" "2,1,1,2,2")
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(set_attr "cc" "none,set_zn,set_zn,none,none")])
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;; Insert bit $2.$3 into $0.$1
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(define_insn "*insv.extract"
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[(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
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(const_int 1)
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(match_operand:QI 1 "const_0_to_7_operand" "n"))
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(any_extract:QI (match_operand:QI 2 "register_operand" "r")
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(const_int 1)
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(match_operand:QI 3 "const_0_to_7_operand" "n")))]
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""
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"bst %2,%3\;bld %0,%1"
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[(set_attr "length" "2")
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(set_attr "cc" "none")])
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;; Insert bit $2.$3 into $0.$1
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(define_insn "*insv.shiftrt"
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[(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
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(const_int 1)
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(match_operand:QI 1 "const_0_to_7_operand" "n"))
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(any_shiftrt:QI (match_operand:QI 2 "register_operand" "r")
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(match_operand:QI 3 "const_0_to_7_operand" "n")))]
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""
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"bst %2,%3\;bld %0,%1"
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[(set_attr "length" "2")
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(set_attr "cc" "none")])
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;; Same, but with a NOT inverting the source bit.
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;; Insert bit ~$2.$3 into $0.$1
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(define_insn "*insv.not-shiftrt"
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[(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
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(const_int 1)
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(match_operand:QI 1 "const_0_to_7_operand" "n"))
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(not:QI (any_shiftrt:QI (match_operand:QI 2 "register_operand" "r")
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(match_operand:QI 3 "const_0_to_7_operand" "n"))))]
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""
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{
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return avr_out_insert_notbit (insn, operands, NULL_RTX, NULL);
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}
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[(set_attr "adjust_len" "insv_notbit")
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(set_attr "cc" "clobber")])
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;; Insert bit ~$2.0 into $0.$1
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(define_insn "*insv.xor1-bit.0"
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[(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
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(const_int 1)
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(match_operand:QI 1 "const_0_to_7_operand" "n"))
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(xor:QI (match_operand:QI 2 "register_operand" "r")
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(const_int 1)))]
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""
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{
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return avr_out_insert_notbit (insn, operands, const0_rtx, NULL);
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}
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[(set_attr "adjust_len" "insv_notbit_0")
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(set_attr "cc" "clobber")])
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;; Insert bit ~$2.0 into $0.$1
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(define_insn "*insv.not-bit.0"
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[(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
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(const_int 1)
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(match_operand:QI 1 "const_0_to_7_operand" "n"))
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(not:QI (match_operand:QI 2 "register_operand" "r")))]
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""
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{
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return avr_out_insert_notbit (insn, operands, const0_rtx, NULL);
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}
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[(set_attr "adjust_len" "insv_notbit_0")
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(set_attr "cc" "clobber")])
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;; Insert bit ~$2.7 into $0.$1
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(define_insn "*insv.not-bit.7"
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[(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
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(const_int 1)
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(match_operand:QI 1 "const_0_to_7_operand" "n"))
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(ge:QI (match_operand:QI 2 "register_operand" "r")
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(const_int 0)))]
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""
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{
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return avr_out_insert_notbit (insn, operands, GEN_INT (7), NULL);
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}
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[(set_attr "adjust_len" "insv_notbit_7")
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(set_attr "cc" "clobber")])
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;; Insert bit ~$2.$3 into $0.$1
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(define_insn "*insv.xor-extract"
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[(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
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(const_int 1)
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(match_operand:QI 1 "const_0_to_7_operand" "n"))
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(any_extract:QI (xor:QI (match_operand:QI 2 "register_operand" "r")
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(match_operand:QI 4 "const_int_operand" "n"))
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(const_int 1)
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(match_operand:QI 3 "const_0_to_7_operand" "n")))]
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"INTVAL (operands[4]) & (1 << INTVAL (operands[3]))"
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{
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return avr_out_insert_notbit (insn, operands, NULL_RTX, NULL);
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}
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[(set_attr "adjust_len" "insv_notbit")
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(set_attr "cc" "clobber")])
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;; Some combine patterns that try to fix bad code when a value is composed
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;; from byte parts like in PR27663.
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