Follow the same practice as other places in ira.c, where
free_dominance_info is called along with loop_optimizer_finalize. Not
doing so causes an ICE on gcc-5-branch, so avoid that possibility on
trunk.
PR rtl-optimization/71275
* ira.c (ira): Free dominance info.
From-SVN: r236843
* config/visium/visium-protos.h (split_double_move): Rename into...
(visium_split_double_move): ...this.
(visium_split_double_add): Declare.
* config/visium/visium.c (split_double_move): Rename into...
(visium_split_double_move): ...this.
(visium_split_double_add): New function.
(visium_expand_copysign): Renumber operands for consistency.
* config/visium/visium.md (DImode move splitter): Adjust to renaming.
(DFmode move splitter): Likewise.
(*addi3_insn): Split by means of visium_split_double_add.
(*adddi3_insn_flags): Delete.
(*plus_plus_sltu<subst_arith>): New insn.
(*subdi3_insn): Split by means of visium_split_double_add.
(subdi3_insn_flags): Delete.
(*minus_minus_sltu<subst_arith>): New insn.
(*negdi2_insn): Split by means of visium_split_double_add.
(*negdi2_insn_flags): Delete.
From-SVN: r236827
* configure.ac: Treat a --with-headers option without argument
the same as the default (i.e. consult sys-include directory).
* configure: Regenerate.
From-SVN: r236825
gcc/ChangeLog:
* combine.c (make_compound_operation): Take known zero bits into
account when checking for possible zero_extend.
gcc/testsuite/ChangeLog:
* gcc.dg/zero_bits_compound-1.c: New test.
* gcc.dg/zero_bits_compound-2.c: New test.
From-SVN: r236813
* config/aarch64/aarch64.md (ashl<mode>3, SHORT modes):
Use const_int_operand for operand 2 predicate. Simplify expand code
as a result.
From-SVN: r236812
[gcc]
2016-05-26 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_emit_p9_fp_minmax): New function
for ISA 3.0 min/max support.
(rs6000_emit_p9_fp_cmove): New function for ISA 3.0 floating point
conditional move support.
(rs6000_emit_cmove): Call rs6000_emit_p9_fp_minmax and
rs6000_emit_p9_fp_cmove if the ISA 3.0 instructions are
available.
* config/rs6000/rs6000.md (SFDF2): New iterator to allow doing
conditional moves where the comparison type is different from move
type.
(fp_minmax): New code iterator for smin/smax.
(minmax): New code attributes for min/max.
(SMINMAX): Likewise.
(smax<mode>3): Combine min, max insns into one insn using the
fp_minmax code iterator. Add support for ISA 3.0 min/max
instructions that don't need -ffast-math.
(s<minmax><mode>3): Likewise.
(smax<mode>3_vsx): Likewise.
(smin<mode>3): Likewise.
(s<minmax><mode>3_vsx): Likewise.
(smin<mode>3_vsx): Likewise.
(pre-VSX min/max splitters): Likewise.
(s<minmax><mode>3_fpr): Likewise.
(movsfcc): Rewrite floating point conditional moves to combine
SFmode/DFmode into a single insn.
(mov<mode>cc): Likewise.
(movdfcc): Likewise.
(fselsfsf4): Combine FSEL cases into a single insn, using SFDF and
SFDF2 iterators to handle all combinations.
(fseldfsf4): Likewise.
(fsel<SFDF:mode><SFDF2:mode>4): Likewise.
(fseldfdf4): Likewise.
(fselsfdf4): Likewise.
(mov<SFDF:mode><SFDF2:mode>cc_p9): Add support for the ISA 3.0
comparison instructions that set a 0/-1 mask, and use it for
floating point conditional move via XXSEL.
(fpmask<mode>): Likewise.
(xxsel<mode>): Likewise.
* config/rs6000/predicates.md (min_max_operator): Delete, no
longer used.
(fpmask_comparison_operaton): New insn for ISA 3.0 comparison
instructions that generate a 0/-1 mask for use with XXSEL.
* config/rs6000/rs6000.h (TARGET_MINMAX_SF): New helper macros to
say whether floating point min/max is available, either through
FSEL, ISA 2.06 min/max, and ISA 3.0 min/max instrucitons.
(TARGET_MINMAX_DF): Likewise.
[gcc/testsuite]
2016-05-26 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/p9-minmax-1.c: New tests for ISA 3.0
floating point min/max/comparison instructions.
* gcc.target/powerpc/p9-minmax-2.c: Likewise.
From-SVN: r236795
PR rtl-optimization/71275
* ira.c (ira): Call loop_optimizer_init to set up bb_loop_depth
for update_equiv_regs and combine_and_move_insns.
From-SVN: r236789
tree-ssa-loop-ivopts.c:loop_body_includes_call was treating internal
calls such as IFN_SQRT as clobbering all caller-saved registers, which
I don't think is appropriate for any current internal function.
Tested on aarch64-linux-gnu and x86_64-linux-gnu.
gcc/
* tree-ssa-loop-ivopts.c (loop_body_includes_call): Don't assume
that internal functions will clobber all caller-saved registers.
From-SVN: r236780
GCC expands switch statements in a very simplistic way and tries to use a table
expansion even when it is a bad idea for performance or codesize.
GCC typically emits extremely sparse tables that contain mostly default entries
(something which currently cannot be tuned by backends). Additionally the
computation of the minimum/maximum label offsets is too simplistic so the
tables are often twice as large as necessary.
The cost of a table switch is significant due to the setup overhead, the table
lookup (which due to being sparse and large adds unnecessary cachemisses)
and hard to predict indirect jump. Therefore it is best to avoid using a table
unless there are many real case labels.
This patch fixes that by setting the default aarch64_case_values_threshold to
16 when the per-CPU tuning is not set. On SPEC2006 this improves the switch
heavy benchmarks GCC and perlbench both in performance (1-2%) as well as size
(0.5-1% smaller).
gcc/
* config/aarch64/aarch64.c (aarch64_case_values_threshold):
Return a better case_values_threshold when optimizing.
From-SVN: r236771
so increase the cost of integer registers slightly to avoid unnecessary int<->FP
moves. This improves register allocation of scalar SIMD operations.
* config/aarch64/aarch64-simd.md (aarch64_combinez):
Add ? to integer variant.
(aarch64_combinez_be): Likewise.
From-SVN: r236770
* config/i386/sse.md (*vcvtps2ph_store<mask_name>): Use v constraint
instead of x constraint.
(vcvtps2ph256<mask_name>): Likewise.
* gcc.target/i386/avx512vl-vcvtps2ph-3.c: New test.
From-SVN: r236765
(<mask_codefor>avx512vl_shuf_<shuffletype>32x4_1<mask_name>): Rename
to ...
(avx512vl_shuf_<shuffletype>32x4_1<mask_name>): ... this.
(*avx_vperm_broadcast_v4sf): Use v constraint instead of x. Use
maybe_evex prefix instead of vex.
(*avx_vperm_broadcast_<mode>): Use v constraint instead of x. Handle
EXT_REX_SSE_REG_P (op0) case in the splitter.
* gcc.target/i386/avx512vl-vbroadcast-3.c: New test.
From-SVN: r236763
This patch adds support for the vec_cmpne altivec builtins from the Power
Architecture 64-Bit ELF V2 ABI OpenPOWER ABI for Linux Supplement (16 July
2015 Version 1.1). There are many of the builtins that are missing and this
is part of a series of patches to add them.
There aren't instructions for vec_cmpne so the output code is built from other
built-ins that do have instructions which in this case is the following.
vec_cmpneq (va, vb) == vec_nor (vec_cmpeq (va, vb), vec_cmpeq (va, vb))
The new test cases are executable tests which verify that the generated
code produces expected values. C macros were used so that the same
test case could be used for both the signed and unsigned versions of various
basic types. A separate executable test case is used for the long long versions
of vec_cmpne because of some differences in loading and storing the vectors.
[gcc]
2016-05-25 Bill Seurer <seurer@linux.vnet.ibm.com>
* config/rs6000/altivec.h (vec_cmpne): Add #define for vec_cmpne.
* config/rs6000/rs6000-builtin.def (vec_cmpne): Add vec_cmpne as a
special case builtin.
* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Add
code for ALTIVEC_BUILTIN_VEC_CMPNE.
* config/rs6000/rs6000.c (altivec_init_builtins): Add definition
for __builtin_vec_cmpne.
[gcc/testsuite]
2016-05-25 Bill Seurer <seurer@linux.vnet.ibm.com>
* gcc.target/powerpc/vec-cmpne.c: New test.
* gcc.target/powerpc/vec-cmpne-long.c: New test.
From-SVN: r236753
* tree-ssa-phiopt.c (factor_out_conditional_conversion): Remove
redundant test and bail out if the type of the new operand is not
a GIMPLE register type after stripping a VIEW_CONVERT_EXPR.
From-SVN: r236748
PR rtl-optimization/66940
* ifcvt.c (noce_get_alt_condition): Check that incrementing or
decrementing desired_val will not overflow before performing these
operations.
* gcc.c-torture/execute/pr66940.c: New test.
From-SVN: r236728
* config/msp430/msp430.c (msp430_attr): Produce an error if a
static interrupt handler is detected.
* config/msp430/msp430.h (LIB_SPEC): Do not use msp430.ld as the
default linker script.
* config/msp430/msp430.md (movpsihi2_lo): New pattern for loading
the low part of a symbolic pointer.
From-SVN: r236704
2016-05-25 Richard Biener <rguenther@suse.de>
PR tree-optimization/71261
* tree-if-conv.c (ifcvt_split_def_stmt): Walk uses on the
interesting stmt instead of immediate uses when looking
for the use operand to replace.
* c-c++-common/torture/pr71261.c: New testcase.
From-SVN: r236701
2016-05-25 Richard Biener <rguenther@suse.de>
PR tree-optimization/71264
* tree-vect-stmts.c (vect_init_vector): Properly deal with
vector type val.
* gcc.dg/vect/pr71264.c: New testcase.
From-SVN: r236699
Fix PR tree-optimization/71239.
* g++.dg/pr71239.C: New test.
PR tree-optimization/71239
* tree.c (array_at_struct_end_p): Do not call operand_equal_p
if DECL_SIZE is NULL.
From-SVN: r236696
2016-05-25 Richard Biener <rguenther@suse.de>
* timevar.def (TV_TREE_LOOP_IFCVT): Add.
* tree-if-conv.c (pass_data_if_conversion): Use it.
From-SVN: r236695
[gcc]
2016-05-24 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/altivec.md (VNEG iterator): New iterator for
VNEGW/VNEGD instructions.
(p9_neg<mode>2): New insns for ISA 3.0 VNEGW/VNEGD.
(neg<mode>2): Add expander for V2DImode added in ISA 2.06, and
support for ISA 3.0 VNEGW/VNEGD instructions.
[gcc/testsuite]
2016-05-24 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/p9-vneg.c: New test for ISA 3.0 VNEGW/VNEGD
instructions.
From-SVN: r236679
gcc/ChangeLog:
2016-05-24 Martin Sebor <msebor@redhat.com>
PR c++/71147
* gcc/tree.h (complete_or_array_type_p): New inline function.
gcc/testsuite/ChangeLog:
2016-05-24 Martin Sebor <msebor@redhat.com>
PR c++/71147
* g++.dg/ext/flexary16.C: New test.
gcc/cp/ChangeLog:
2016-05-24 Martin Sebor <msebor@redhat.com>
PR c++/71147
* decl.c (layout_var_decl, grokdeclarator): Use complete_or_array_type_p.
* pt.c (instantiate_class_template_1): Try to complete the element
type of a flexible array member.
(can_complete_type_without_circularity): Handle arrays of unknown bound.
* typeck.c (complete_type): Also complete the type of the elements of
arrays with an unspecified bound.
From-SVN: r236664
* config/i386/i386.h (TARGET_AVOID_4BYTE_PREFIXES): Define.
* config/i386/constraints.md (Yr): Test TARGET_AVOID_4BYTE_PREFIXES
rather than X86_TUNE_AVOID_4BYTE_PREFIXES.
From-SVN: r236662
* config/i386/sse.md (<sse4_1>_round<ssemodesuffix><avxsizesuffix>):
Limit 1st alternative to noavx isa, split 2nd alternative into one
noavx and one avx alternative, use *x and Bm in the former and
x and m in the latter.
From-SVN: r236661
* config/i386/sse.md (vec_set<mode>_0): Use sse4_noavx isa instead
of sse4 for the first alternative, drop %v from the template
and d operand modifier. Split second alternative into one sse4_noavx
and one avx alternative, use *x instead of *v in the former and v
instead of *v in the latter.
(*sse4_1_extractps): Use noavx isa instead of * for the first
alternative, drop %v from the template. Split second alternative into
one noavx and one avx alternative, use *x instead of *v in the
former and v instead of *v in the latter.
(<vi8_sse4_1_avx2_avx512>_movntdqa): Guard the first 2 alternatives
with noavx and the last one with avx.
(sse4_1_phminposuw): Guard first alternative with noavx isa,
split the second one into one noavx and one avx alternative,
use *x and Bm in the former and x and m in the latter one.
(<sse4_1>_ptest<mode>): Use noavx instead of * for the first two
alternatives.
From-SVN: r236660
* config/i386/sse.md (sse4_1_<code>v8qiv8hi2<mask_name>): Limit
first two alternatives to noavx, use *x instead of *v in the second
one, add avx alternative without *.
(sse4_1_<code>v4qiv4si2<mask_name>, sse4_1_<code>v4hiv4si2<mask_name>,
sse4_1_<code>v2qiv2di2<mask_name>, sse4_1_<code>v2hiv2di2<mask_name>,
sse4_1_<code>v2siv2di2<mask_name>): Likewise.
From-SVN: r236659
Alan Modra