mirror of git://gcc.gnu.org/git/gcc.git
111 lines
2.8 KiB
C++
111 lines
2.8 KiB
C++
// locks.h - Thread synchronization primitives. PA-RISC implementation.
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/* Copyright (C) 2002, 2005 Free Software Foundation
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This file is part of libgcj.
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This software is copyrighted work licensed under the terms of the
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Libgcj License. Please consult the file "LIBGCJ_LICENSE" for
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details. */
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#ifndef __SYSDEP_LOCKS_H__
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#define __SYSDEP_LOCKS_H__
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// Integer type big enough for object address.
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typedef size_t obj_addr_t;
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template<int _Inst>
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struct _pa_jv_cas_lock
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{
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static volatile int _S_pa_jv_cas_lock;
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};
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template<int _Inst>
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volatile int
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_pa_jv_cas_lock<_Inst>::_S_pa_jv_cas_lock __attribute__ ((aligned (16))) = 1;
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// Because of the lack of weak support when using the hpux som
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// linker, we explicitly instantiate the atomicity lock.
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template volatile int _pa_jv_cas_lock<0>::_S_pa_jv_cas_lock;
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// Atomically replace *addr by new_val if it was initially equal to old_val.
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// Return true if the comparison is successful.
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// Assumed to have acquire semantics, i.e. later memory operations
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// cannot execute before the compare_and_swap finishes.
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// The following implementation is atomic but it can deadlock
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// (e.g., if a thread dies holding the lock).
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inline static bool
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__attribute__ ((__unused__))
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compare_and_swap(volatile obj_addr_t *addr,
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obj_addr_t old_val,
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obj_addr_t new_val)
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{
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bool result;
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int tmp;
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volatile int& lock = _pa_jv_cas_lock<0>::_S_pa_jv_cas_lock;
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__asm__ __volatile__ ("ldcw 0(%1),%0\n\t"
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"cmpib,<>,n 0,%0,.+20\n\t"
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"ldw 0(%1),%0\n\t"
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"cmpib,= 0,%0,.-4\n\t"
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"nop\n\t"
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"b,n .-20"
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: "=&r" (tmp)
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: "r" (&lock)
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: "memory");
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if (*addr != old_val)
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result = false;
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else
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{
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*addr = new_val;
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result = true;
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}
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/* Reset lock with PA 2.0 "ordered" store. */
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__asm__ __volatile__ ("stw,ma %1,0(%0)"
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: : "r" (&lock), "r" (tmp) : "memory");
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return result;
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}
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// Set *addr to new_val with release semantics, i.e. making sure
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// that prior loads and stores complete before this
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// assignment.
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inline static void
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release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
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{
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__asm__ __volatile__(" " : : : "memory");
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*(addr) = new_val;
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}
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// Compare_and_swap with release semantics instead of acquire semantics.
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// On many architecture, the operation makes both guarantees, so the
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// implementation can be the same.
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inline static bool
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compare_and_swap_release(volatile obj_addr_t *addr,
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obj_addr_t old,
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obj_addr_t new_val)
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{
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return compare_and_swap(addr, old, new_val);
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}
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// Ensure that subsequent instructions do not execute on stale
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// data that was loaded from memory before the barrier.
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inline static void
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read_barrier()
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{
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__asm__ __volatile__(" " : : : "memory");
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}
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// Ensure that prior stores to memory are completed with respect to other
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// processors.
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inline static void
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write_barrier()
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{
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__asm__ __volatile__(" " : : : "memory");
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}
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#endif
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