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			216 lines
		
	
	
		
			6.7 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			216 lines
		
	
	
		
			6.7 KiB
		
	
	
	
		
			C
		
	
	
	
| /* DWARF2 EH unwinding support for SPARC Linux.
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|    Copyright (C) 2004-2019 Free Software Foundation, Inc.
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| 
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| This file is part of GCC.
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| 
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| GCC is free software; you can redistribute it and/or modify
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| it under the terms of the GNU General Public License as published by
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| the Free Software Foundation; either version 3, or (at your option)
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| any later version.
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| 
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| GCC is distributed in the hope that it will be useful,
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| but WITHOUT ANY WARRANTY; without even the implied warranty of
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| MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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| GNU General Public License for more details.
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| 
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| Under Section 7 of GPL version 3, you are granted additional
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| permissions described in the GCC Runtime Library Exception, version
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| 3.1, as published by the Free Software Foundation.
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| 
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| You should have received a copy of the GNU General Public License and
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| a copy of the GCC Runtime Library Exception along with this program;
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| see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
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| <http://www.gnu.org/licenses/>.  */
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| 
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| /* Do code reading to identify a signal frame, and set the frame
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|    state data appropriately.  See unwind-dw2.c for the structs.  */
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| 
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| #if defined(__arch64__)
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| 
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| #undef STACK_BIAS
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| #define STACK_BIAS 2047
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| 
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| /* 64-bit SPARC version */
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| #define MD_FALLBACK_FRAME_STATE_FOR sparc64_fallback_frame_state
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| 
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| static _Unwind_Reason_Code
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| sparc64_fallback_frame_state (struct _Unwind_Context *context,
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| 			      _Unwind_FrameState *fs)
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| {
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|   unsigned int *pc = context->ra;
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|   long this_cfa = (long) context->cfa;
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|   long new_cfa, ra_location, shifted_ra_location;
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|   long regs_off, fpu_save_off;
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|   long fpu_save;
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|   int i;
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| 
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|   if (pc[0] != 0x82102065	/* mov NR_rt_sigreturn, %g1 */
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|       || pc[1] != 0x91d0206d)	/* ta 0x6d */
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|     return _URC_END_OF_STACK;
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| 
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|   regs_off = 192 + 128;
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|   fpu_save_off = regs_off + (16 * 8) + (3 * 8) + (2 * 4);
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| 
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|   new_cfa = *(long *)(this_cfa + regs_off + (14 * 8));
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|   /* The frame address is %sp + STACK_BIAS in 64-bit mode.  */
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|   new_cfa += STACK_BIAS;
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|   fpu_save = *(long *)(this_cfa + fpu_save_off);
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|   fs->regs.cfa_how = CFA_REG_OFFSET;
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|   fs->regs.cfa_reg = __builtin_dwarf_sp_column ();
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|   fs->regs.cfa_offset = new_cfa - this_cfa;
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| 
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|   for (i = 1; i < 16; i++)
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|     {
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|       /* We never restore %sp as everything is purely CFA-based.  */
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|       if ((unsigned int) i == __builtin_dwarf_sp_column ())
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| 	continue;
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| 
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|       fs->regs.reg[i].how = REG_SAVED_OFFSET;
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|       fs->regs.reg[i].loc.offset
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| 	= this_cfa + regs_off + (i * 8) - new_cfa;
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|     }
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|   for (i = 0; i < 16; i++)
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|     {
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|       fs->regs.reg[i + 16].how = REG_SAVED_OFFSET;
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|       fs->regs.reg[i + 16].loc.offset
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| 	= this_cfa + (i * 8) - new_cfa;
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|     }
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|   if (fpu_save)
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|     {
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|       for (i = 0; i < 64; i++)
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| 	{
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| 	  if (i > 32 && (i & 0x1))
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| 	    continue;
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| 	  fs->regs.reg[i + 32].how = REG_SAVED_OFFSET;
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| 	  fs->regs.reg[i + 32].loc.offset
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| 	    = fpu_save + (i * 4) - new_cfa;
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| 	}
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|     }
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| 
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|   /* State the rules to find the kernel's code "return address", which is
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|      the address of the active instruction when the signal was caught.
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|      On the SPARC, since RETURN_ADDR_OFFSET (essentially 8) is defined, we
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|      need to preventively subtract it from the purported return address.  */
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|   ra_location = this_cfa + regs_off + 17 * 8;
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|   shifted_ra_location = this_cfa + regs_off + 19 * 8; /* Y register */
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|   *(long *)shifted_ra_location = *(long *)ra_location - 8;
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|   fs->retaddr_column = 0;
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|   fs->regs.reg[0].how = REG_SAVED_OFFSET;
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|   fs->regs.reg[0].loc.offset = shifted_ra_location - new_cfa;
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|   fs->signal_frame = 1;
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| 
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|   return _URC_NO_REASON;
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| }
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| 
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| #define MD_FROB_UPDATE_CONTEXT sparc64_frob_update_context
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| 
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| static void
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| sparc64_frob_update_context (struct _Unwind_Context *context,
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| 			     _Unwind_FrameState *fs)
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| {
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|   /* The column of %sp contains the old CFA, not the old value of %sp.
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|      The CFA offset already comprises the stack bias so, when %sp is the
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|      CFA register, we must avoid counting the stack bias twice.  Do not
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|      do that for signal frames as the offset is artificial for them.  */
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|   if (fs->regs.cfa_reg == __builtin_dwarf_sp_column ()
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|       && fs->regs.cfa_how == CFA_REG_OFFSET
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|       && fs->regs.cfa_offset != 0
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|       && !fs->signal_frame)
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|     {
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|       long i;
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| 
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|       context->cfa -= STACK_BIAS;
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| 
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|       for (i = 0; i < __LIBGCC_DWARF_FRAME_REGISTERS__ + 1; ++i)
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| 	if (fs->regs.reg[i].how == REG_SAVED_OFFSET)
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| 	  _Unwind_SetGRPtr (context, i,
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| 			    _Unwind_GetGRPtr (context, i) - STACK_BIAS);
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|     }
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| }
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| 
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| #else
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| 
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| /* 32-bit SPARC version */
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| #define MD_FALLBACK_FRAME_STATE_FOR sparc_fallback_frame_state
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| 
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| static _Unwind_Reason_Code
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| sparc_fallback_frame_state (struct _Unwind_Context *context,
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| 			    _Unwind_FrameState *fs)
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| {
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|   unsigned int *pc = context->ra;
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|   int this_cfa = (int) context->cfa;
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|   int new_cfa, ra_location, shifted_ra_location;
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|   int regs_off, fpu_save_off;
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|   int fpu_save;
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|   int old_style, i;
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| 
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|   if (pc[1] != 0x91d02010)	/* ta 0x10 */
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|     return _URC_END_OF_STACK;
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| 
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|   if (pc[0] == 0x821020d8)	/* mov NR_sigreturn, %g1 */
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|     old_style = 1;
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|   else if (pc[0] == 0x82102065)	/* mov NR_rt_sigreturn, %g1 */
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|     old_style = 0;
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|   else
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|     return _URC_END_OF_STACK;
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| 
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|   if (old_style)
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|     {
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|       regs_off = 96;
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|       fpu_save_off = regs_off + (4 * 4) + (16 * 4);
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|     }
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|   else
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|     {
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|       regs_off = 96 + 128;
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|       fpu_save_off = regs_off + (4 * 4) + (16 * 4) + (2 * 4);
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|     }
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| 
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|   new_cfa = *(int *)(this_cfa + regs_off + (4 * 4) + (14 * 4));
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|   fpu_save = *(int *)(this_cfa + fpu_save_off);
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|   fs->regs.cfa_how = CFA_REG_OFFSET;
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|   fs->regs.cfa_reg = __builtin_dwarf_sp_column ();
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|   fs->regs.cfa_offset = new_cfa - this_cfa;
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| 
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|   for (i = 1; i < 16; i++)
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|     {
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|       /* We never restore %sp as everything is purely CFA-based.  */
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|       if ((unsigned int) i == __builtin_dwarf_sp_column ())
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| 	continue;
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| 
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|       fs->regs.reg[i].how = REG_SAVED_OFFSET;
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|       fs->regs.reg[i].loc.offset
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| 	= this_cfa + regs_off + (4 * 4) + (i * 4) - new_cfa;
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|     }
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|   for (i = 0; i < 16; i++)
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|     {
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|       fs->regs.reg[i + 16].how = REG_SAVED_OFFSET;
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|       fs->regs.reg[i + 16].loc.offset
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| 	= this_cfa + (i * 4) - new_cfa;
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|     }
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|   if (fpu_save)
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|     {
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|       for (i = 0; i < 32; i++)
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| 	{
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| 	  fs->regs.reg[i + 32].how = REG_SAVED_OFFSET;
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| 	  fs->regs.reg[i + 32].loc.offset
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| 	    = fpu_save + (i * 4) - new_cfa;
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| 	}
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|     }
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| 
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|   /* State the rules to find the kernel's code "return address", which is
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|      the address of the active instruction when the signal was caught.
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|      On the SPARC, since RETURN_ADDR_OFFSET (essentially 8) is defined, we
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|      need to preventively subtract it from the purported return address.  */
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|   ra_location = this_cfa + regs_off + 4;
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|   shifted_ra_location = this_cfa + regs_off + 3 * 4; /* Y register */
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|   *(int *)shifted_ra_location = *(int *)ra_location - 8;
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|   fs->retaddr_column = 0;
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|   fs->regs.reg[0].how = REG_SAVED_OFFSET;
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|   fs->regs.reg[0].loc.offset = shifted_ra_location - new_cfa;
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|   fs->signal_frame = 1;
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| 
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|   return _URC_NO_REASON;
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| }
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| 
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| #endif
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