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drm/amd/display: Get DMUB registers from ASIC specific structs

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[Why]
These values can differ per ASIC and should follow the full DC style
register programming model.

[How]
Define a common list and fill in the common list separately for
dcn20 and dcn21.

Unlike DC we're not using designated initializers for better compiler
compatibility since this resides in the DMUB service.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Nicholas Kazlauskas
2019-11-20 09:29:17 -05:00
committed by Alex Deucher
parent 6b5d7730d2
commit 01c229d977
7 changed files with 176 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
View File

@@ -25,6 +25,7 @@
#include "../inc/dmub_srv.h"
#include "dmub_reg.h"
#include "dmub_dcn20.h"
#include "dcn/dcn_2_0_0_offset.h"
#include "dcn/dcn_2_0_0_sh_mask.h"
@@ -33,6 +34,25 @@
#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
#define CTX dmub
#define REGS dmub->regs
/* Registers. */
const struct dmub_srv_common_regs dmub_srv_dcn20_regs = {
#define DMUB_SR(reg) REG_OFFSET(reg),
{ DMUB_COMMON_REGS() },
#undef DMUB_SR
#define DMUB_SF(reg, field) FD_MASK(reg, field),
{ DMUB_COMMON_FIELDS() },
#undef DMUB_SF
#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
{ DMUB_COMMON_FIELDS() },
#undef DMUB_SF
};
/* Shared functions. */
void dmub_dcn20_reset(struct dmub_srv *dmub)
{
@@ -47,8 +67,9 @@ void dmub_dcn20_reset_release(struct dmub_srv *dmub)
REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 0);
}
void dmub_dcn20_backdoor_load(struct dmub_srv *dmub, struct dmub_window *cw0,
struct dmub_window *cw1)
void dmub_dcn20_backdoor_load(struct dmub_srv *dmub,
const struct dmub_window *cw0,
const struct dmub_window *cw1)
{
REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x4,