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Merge branch '20240602114439.1611-1-quic_jkona@quicinc.com' into clk-for-6.11

Browse Source 
Merge SM8650 video and camera clock drivers through topic branch, to
make available the DeviceTree binding includes to the DeviceTree source
branches as well.
This commit is contained in:
Bjorn Andersson
2024-06-25 18:06:44 -05:00
parent 211681998d 09ea421652
commit 03675e398b
8 changed files with 3979 additions and 8 deletions
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8
drivers/clk/qcom/Kconfig
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@@ -848,6 +848,14 @@ config SM_CAMCC_8550
Support for the camera clock controller on SM8550 devices.
Say Y if you want to support camera devices and camera functionality.
config SM_CAMCC_8650
tristate "SM8650 Camera Clock Controller"
depends on ARM64 || COMPILE_TEST
select SM_GCC_8650
help
Support for the camera clock controller on SM8650 devices.
Say Y if you want to support camera devices and camera functionality.
config SM_DISPCC_6115
tristate "SM6115 Display Clock Controller"
depends on ARM64 || COMPILE_TEST

1
drivers/clk/qcom/Makefile
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@@ -112,6 +112,7 @@ obj-$(CONFIG_SM_CAMCC_7150) += camcc-sm7150.o
obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o
obj-$(CONFIG_SM_CAMCC_8550) += camcc-sm8550.o
obj-$(CONFIG_SM_CAMCC_8650) += camcc-sm8650.o
obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o
obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o
obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o

3591
drivers/clk/qcom/camcc-sm8650.c Normal file
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File diff suppressed because it is too large Load Diff

156
drivers/clk/qcom/videocc-sm8550.c
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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/clk-provider.h>
@@ -10,7 +10,7 @@
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm8450-videocc.h>
#include <dt-bindings/clock/qcom,sm8650-videocc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
@@ -35,7 +35,7 @@ static const struct pll_vco lucid_ole_vco[] = {
{ 249600000, 2300000000, 0 },
};
static const struct alpha_pll_config video_cc_pll0_config = {
static struct alpha_pll_config video_cc_pll0_config = {
.l = 0x25,
.alpha = 0x8000,
.config_ctl_val = 0x20485699,
@@ -66,7 +66,7 @@ static struct clk_alpha_pll video_cc_pll0 = {
},
};
static const struct alpha_pll_config video_cc_pll1_config = {
static struct alpha_pll_config video_cc_pll1_config = {
.l = 0x36,
.alpha = 0xb000,
.config_ctl_val = 0x20485699,
@@ -117,6 +117,14 @@ static const struct clk_parent_data video_cc_parent_data_1[] = {
{ .hw = &video_cc_pll1.clkr.hw },
};
static const struct parent_map video_cc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data video_cc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
};
static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
@@ -126,6 +134,16 @@ static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
{ }
};
static const struct freq_tbl ftbl_video_cc_mvs0_clk_src_sm8650[] = {
F(588000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(900000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1140000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1305000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1440000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_mvs0_clk_src = {
.cmd_rcgr = 0x8000,
.mnd_width = 0,
@@ -149,6 +167,15 @@ static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
{ }
};
static const struct freq_tbl ftbl_video_cc_mvs1_clk_src_sm8650[] = {
F(840000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
F(1110000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_mvs1_clk_src = {
.cmd_rcgr = 0x8018,
.mnd_width = 0,
@@ -164,6 +191,26 @@ static struct clk_rcg2 video_cc_mvs1_clk_src = {
},
};
static const struct freq_tbl ftbl_video_cc_xo_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 video_cc_xo_clk_src = {
.cmd_rcgr = 0x810c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = video_cc_parent_map_2,
.freq_tbl = ftbl_video_cc_xo_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "video_cc_xo_clk_src",
.parent_data = video_cc_parent_data_2,
.num_parents = ARRAY_SIZE(video_cc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
.reg = 0x80c4,
.shift = 0,
@@ -244,6 +291,26 @@ static struct clk_branch video_cc_mvs0_clk = {
},
};
static struct clk_branch video_cc_mvs0_shift_clk = {
.halt_reg = 0x8128,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8128,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x8128,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs0c_clk = {
.halt_reg = 0x8064,
.halt_check = BRANCH_HALT,
@@ -262,6 +329,26 @@ static struct clk_branch video_cc_mvs0c_clk = {
},
};
static struct clk_branch video_cc_mvs0c_shift_clk = {
.halt_reg = 0x812c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x812c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x812c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs0c_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs1_clk = {
.halt_reg = 0x80e0,
.halt_check = BRANCH_HALT_SKIP,
@@ -282,6 +369,26 @@ static struct clk_branch video_cc_mvs1_clk = {
},
};
static struct clk_branch video_cc_mvs1_shift_clk = {
.halt_reg = 0x8130,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8130,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x8130,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch video_cc_mvs1c_clk = {
.halt_reg = 0x8090,
.halt_check = BRANCH_HALT,
@@ -300,6 +407,26 @@ static struct clk_branch video_cc_mvs1c_clk = {
},
};
static struct clk_branch video_cc_mvs1c_shift_clk = {
.halt_reg = 0x8134,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x8134,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x8134,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "video_cc_mvs1c_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&video_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc video_cc_mvs0c_gdsc = {
.gdscr = 0x804c,
.en_rest_wait_val = 0x2,
@@ -363,6 +490,7 @@ static struct clk_regmap *video_cc_sm8550_clocks[] = {
[VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
[VIDEO_CC_PLL0] = &video_cc_pll0.clkr,
[VIDEO_CC_PLL1] = &video_cc_pll1.clkr,
[VIDEO_CC_XO_CLK_SRC] = NULL,
};
static struct gdsc *video_cc_sm8550_gdscs[] = {
@@ -380,6 +508,7 @@ static const struct qcom_reset_map video_cc_sm8550_resets[] = {
[CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 },
[VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0x8064, .bit = 2, .udelay = 1000 },
[VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0x8090, .bit = 2, .udelay = 1000 },
[VIDEO_CC_XO_CLK_ARES] = { .reg = 0x8124, .bit = 2, .udelay = 100 },
};
static const struct regmap_config video_cc_sm8550_regmap_config = {
@@ -402,6 +531,7 @@ static struct qcom_cc_desc video_cc_sm8550_desc = {
static const struct of_device_id video_cc_sm8550_match_table[] = {
{ .compatible = "qcom,sm8550-videocc" },
{ .compatible = "qcom,sm8650-videocc" },
{ }
};
MODULE_DEVICE_TABLE(of, video_cc_sm8550_match_table);
@@ -410,6 +540,7 @@ static int video_cc_sm8550_probe(struct platform_device *pdev)
{
struct regmap *regmap;
int ret;
u32 sleep_clk_offset = 0x8140;
ret = devm_pm_runtime_enable(&pdev->dev);
if (ret)
@@ -425,12 +556,27 @@ static int video_cc_sm8550_probe(struct platform_device *pdev)
return PTR_ERR(regmap);
}
if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8650-videocc")) {
sleep_clk_offset = 0x8150;
video_cc_pll0_config.l = 0x1e;
video_cc_pll0_config.alpha = 0xa000;
video_cc_pll1_config.l = 0x2b;
video_cc_pll1_config.alpha = 0xc000;
video_cc_mvs0_clk_src.freq_tbl = ftbl_video_cc_mvs0_clk_src_sm8650;
video_cc_mvs1_clk_src.freq_tbl = ftbl_video_cc_mvs1_clk_src_sm8650;
video_cc_sm8550_clocks[VIDEO_CC_MVS0_SHIFT_CLK] = &video_cc_mvs0_shift_clk.clkr;
video_cc_sm8550_clocks[VIDEO_CC_MVS0C_SHIFT_CLK] = &video_cc_mvs0c_shift_clk.clkr;
video_cc_sm8550_clocks[VIDEO_CC_MVS1_SHIFT_CLK] = &video_cc_mvs1_shift_clk.clkr;
video_cc_sm8550_clocks[VIDEO_CC_MVS1C_SHIFT_CLK] = &video_cc_mvs1c_shift_clk.clkr;
video_cc_sm8550_clocks[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr;
}
clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);
/* Keep some clocks always-on */
qcom_branch_set_clk_en(regmap, 0x80f4); /* VIDEO_CC_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x8140); /* VIDEO_CC_SLEEP_CLK */
qcom_branch_set_clk_en(regmap, sleep_clk_offset); /* VIDEO_CC_SLEEP_CLK */
qcom_branch_set_clk_en(regmap, 0x8124); /* VIDEO_CC_XO_CLK */
ret = qcom_cc_really_probe(&pdev->dev, &video_cc_sm8550_desc, regmap);