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drm/mgag200: Compute PLL values during atomic check

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PLL setup can fail if the display mode's clock is not supported by
any PLL configuration. Compute the PLL values during atomic check, so
that atomic commits can fail at the appropriate time. If successful,
use the values in the atomic-update phase.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20210714142240.21979-14-tzimmermann@suse.de
This commit is contained in:
Thomas Zimmermann
2021-07-14 16:22:40 +02:00
parent 51b569394b
commit 0a6dab7d07
2 changed files with 22 additions and 18 deletions
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2
drivers/gpu/drm/mgag200/mgag200_drv.h
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@@ -159,6 +159,8 @@ struct mgag200_pll {
struct mgag200_crtc_state {
struct drm_crtc_state base;
struct mgag200_pll_values pixpllc;
};
static inline struct mgag200_crtc_state *to_mgag200_crtc_state(struct drm_crtc_state *base)