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drm/amd/display: fix PSR-SU/DSC interoperability support

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Currently, there are issues with enabling PSR-SU + DSC. This stems from
the fact that DSC imposes a slice height on transmitted video data and
we are not conforming to that slice height in PSR-SU regions. So, pass
slice_height into su_y_granularity to feed the DSC slice height into
PSR-SU code.

Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hamza Mahfooz
2023-01-05 10:54:12 -05:00
committed by Alex Deucher
parent 69939009bd
commit 13b90cf900
3 changed files with 37 additions and 0 deletions
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31
drivers/gpu/drm/amd/display/modules/power/power_helpers.c
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@@ -916,3 +916,34 @@ bool mod_power_only_edp(const struct dc_state *context, const struct dc_stream_s
{
return context && context->stream_count == 1 && dc_is_embedded_signal(stream->signal);
}
bool psr_su_set_y_granularity(struct dc *dc, struct dc_link *link,
struct dc_stream_state *stream,
struct psr_config *config)
{
uint16_t pic_height;
uint8_t slice_height;
if ((link->connector_signal & SIGNAL_TYPE_EDP) &&
(!dc->caps.edp_dsc_support ||
link->panel_config.dsc.disable_dsc_edp ||
!link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||
!stream->timing.dsc_cfg.num_slices_v))
return true;
pic_height = stream->timing.v_addressable +
stream->timing.v_border_top + stream->timing.v_border_bottom;
slice_height = pic_height / stream->timing.dsc_cfg.num_slices_v;
if (slice_height) {
if (config->su_y_granularity &&
(slice_height % config->su_y_granularity)) {
ASSERT(0);
return false;
}
config->su_y_granularity = slice_height;
}
return true;
}