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https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
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drm/i915/gvt: Rename file render.{c, h} to mmio_context.{c, h}
Rename the files to reflect their real role - to switch the mmio context of each vGPU engine. v2: update Makefile. Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
This commit is contained in:
Changbin Du
403
drivers/gpu/drm/i915/gvt/mmio_context.c
Normal file
403
drivers/gpu/drm/i915/gvt/mmio_context.c
Normal file
@@ -0,0 +1,403 @@
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/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Eddie Dong <eddie.dong@intel.com>
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* Kevin Tian <kevin.tian@intel.com>
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*
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* Contributors:
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* Zhi Wang <zhi.a.wang@intel.com>
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* Changbin Du <changbin.du@intel.com>
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* Zhenyu Wang <zhenyuw@linux.intel.com>
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* Tina Zhang <tina.zhang@intel.com>
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* Bing Niu <bing.niu@intel.com>
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*
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*/
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#include "i915_drv.h"
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#include "gvt.h"
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#include "trace.h"
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/**
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* Defined in Intel Open Source PRM.
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* Ref: https://01.org/linuxgraphics/documentation/hardware-specification-prms
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*/
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#define TRVATTL3PTRDW(i) _MMIO(0x4de0 + (i)*4)
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#define TRNULLDETCT _MMIO(0x4de8)
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#define TRINVTILEDETCT _MMIO(0x4dec)
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#define TRVADR _MMIO(0x4df0)
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#define TRTTE _MMIO(0x4df4)
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#define RING_EXCC(base) _MMIO((base) + 0x28)
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#define RING_GFX_MODE(base) _MMIO((base) + 0x29c)
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#define VF_GUARDBAND _MMIO(0x83a4)
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/* Raw offset is appened to each line for convenience. */
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static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
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{RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
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{RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
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{RCS, HWSTAM, 0x0, false}, /* 0x2098 */
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{RCS, INSTPM, 0xffff, true}, /* 0x20c0 */
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{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
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{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
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{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
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{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
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{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
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{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
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{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
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{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
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{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
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{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
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{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
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{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
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{RCS, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
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{RCS, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
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{RCS, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
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{RCS, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
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{RCS, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
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{RCS, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
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{BCS, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
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{BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
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{BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
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{BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
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{BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */
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{ /* Terminated */ }
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};
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static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
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{RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
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{RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
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{RCS, HWSTAM, 0x0, false}, /* 0x2098 */
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{RCS, INSTPM, 0xffff, true}, /* 0x20c0 */
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{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
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{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
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{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
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{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
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{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
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{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
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{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
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{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
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{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
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{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
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{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
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{RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
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{RCS, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
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{RCS, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
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{RCS, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
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{RCS, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
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{RCS, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
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{RCS, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
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{RCS, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */
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{RCS, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */
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{RCS, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */
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{RCS, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */
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{RCS, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */
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{RCS, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */
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{RCS, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */
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{RCS, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */
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{RCS, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
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{RCS, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
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{RCS, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
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{RCS, TRVATTL3PTRDW(0), 0, false}, /* 0x4de0 */
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{RCS, TRVATTL3PTRDW(1), 0, false}, /* 0x4de4 */
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{RCS, TRNULLDETCT, 0, false}, /* 0x4de8 */
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{RCS, TRINVTILEDETCT, 0, false}, /* 0x4dec */
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{RCS, TRVADR, 0, false}, /* 0x4df0 */
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{RCS, TRTTE, 0, false}, /* 0x4df4 */
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{BCS, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
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{BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
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{BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
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{BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
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{BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */
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{VCS2, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */
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{VECS, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */
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{RCS, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */
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{RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
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{RCS, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */
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{RCS, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */
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{RCS, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */
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{RCS, GEN9_CSFE_CHICKEN1_RCS, 0x0, false}, /* 0x20d4 */
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{RCS, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
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{RCS, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */
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{RCS, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */
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{ /* Terminated */ }
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};
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static u32 gen9_render_mocs[I915_NUM_ENGINES][64];
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static u32 gen9_render_mocs_L3[32];
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static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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struct intel_vgpu_submission *s = &vgpu->submission;
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enum forcewake_domains fw;
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i915_reg_t reg;
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u32 regs[] = {
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[RCS] = 0x4260,
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[VCS] = 0x4264,
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[VCS2] = 0x4268,
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[BCS] = 0x426c,
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[VECS] = 0x4270,
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};
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if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
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return;
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if (!test_and_clear_bit(ring_id, (void *)s->tlb_handle_pending))
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return;
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reg = _MMIO(regs[ring_id]);
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/* WaForceWakeRenderDuringMmioTLBInvalidate:skl
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* we need to put a forcewake when invalidating RCS TLB caches,
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* otherwise device can go to RC6 state and interrupt invalidation
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* process
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*/
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fw = intel_uncore_forcewake_for_reg(dev_priv, reg,
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FW_REG_READ | FW_REG_WRITE);
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if (ring_id == RCS && (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
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fw |= FORCEWAKE_RENDER;
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intel_uncore_forcewake_get(dev_priv, fw);
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I915_WRITE_FW(reg, 0x1);
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if (wait_for_atomic((I915_READ_FW(reg) == 0), 50))
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gvt_vgpu_err("timeout in invalidate ring (%d) tlb\n", ring_id);
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else
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vgpu_vreg(vgpu, regs[ring_id]) = 0;
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intel_uncore_forcewake_put(dev_priv, fw);
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gvt_dbg_core("invalidate TLB for ring %d\n", ring_id);
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}
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static void load_mocs(struct intel_vgpu *vgpu, int ring_id)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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i915_reg_t offset, l3_offset;
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u32 regs[] = {
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[RCS] = 0xc800,
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[VCS] = 0xc900,
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[VCS2] = 0xca00,
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[BCS] = 0xcc00,
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[VECS] = 0xcb00,
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};
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int i;
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if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
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return;
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offset.reg = regs[ring_id];
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for (i = 0; i < 64; i++) {
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gen9_render_mocs[ring_id][i] = I915_READ_FW(offset);
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I915_WRITE_FW(offset, vgpu_vreg(vgpu, offset));
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offset.reg += 4;
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}
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if (ring_id == RCS) {
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l3_offset.reg = 0xb020;
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for (i = 0; i < 32; i++) {
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gen9_render_mocs_L3[i] = I915_READ_FW(l3_offset);
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I915_WRITE_FW(l3_offset, vgpu_vreg(vgpu, l3_offset));
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l3_offset.reg += 4;
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}
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}
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}
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static void restore_mocs(struct intel_vgpu *vgpu, int ring_id)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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i915_reg_t offset, l3_offset;
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u32 regs[] = {
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[RCS] = 0xc800,
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[VCS] = 0xc900,
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[VCS2] = 0xca00,
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[BCS] = 0xcc00,
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[VECS] = 0xcb00,
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};
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int i;
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if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
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return;
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offset.reg = regs[ring_id];
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for (i = 0; i < 64; i++) {
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vgpu_vreg(vgpu, offset) = I915_READ_FW(offset);
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I915_WRITE_FW(offset, gen9_render_mocs[ring_id][i]);
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offset.reg += 4;
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}
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if (ring_id == RCS) {
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l3_offset.reg = 0xb020;
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for (i = 0; i < 32; i++) {
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vgpu_vreg(vgpu, l3_offset) = I915_READ_FW(l3_offset);
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I915_WRITE_FW(l3_offset, gen9_render_mocs_L3[i]);
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l3_offset.reg += 4;
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}
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}
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}
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#define CTX_CONTEXT_CONTROL_VAL 0x03
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/* Switch ring mmio values (context) from host to a vgpu. */
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static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, int ring_id)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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struct intel_vgpu_submission *s = &vgpu->submission;
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u32 *reg_state = s->shadow_ctx->engine[ring_id].lrc_reg_state;
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u32 ctx_ctrl = reg_state[CTX_CONTEXT_CONTROL_VAL];
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u32 inhibit_mask =
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_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
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struct engine_mmio *mmio;
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u32 v;
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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load_mocs(vgpu, ring_id);
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mmio = vgpu->gvt->engine_mmio_list;
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while (i915_mmio_reg_offset((mmio++)->reg)) {
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if (mmio->ring_id != ring_id)
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continue;
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mmio->value = I915_READ_FW(mmio->reg);
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/*
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* if it is an inhibit context, load in_context mmio
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* into HW by mmio write. If it is not, skip this mmio
|
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* write.
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*/
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if (mmio->in_context &&
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((ctx_ctrl & inhibit_mask) != inhibit_mask) &&
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i915_modparams.enable_execlists)
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continue;
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if (mmio->mask)
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v = vgpu_vreg(vgpu, mmio->reg) | (mmio->mask << 16);
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else
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v = vgpu_vreg(vgpu, mmio->reg);
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I915_WRITE_FW(mmio->reg, v);
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trace_render_mmio(vgpu->id, "load",
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i915_mmio_reg_offset(mmio->reg),
|
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mmio->value, v);
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}
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handle_tlb_pending_event(vgpu, ring_id);
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}
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/* Switch ring mmio values (context) from vgpu to host. */
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static void switch_mmio_to_host(struct intel_vgpu *vgpu, int ring_id)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
|
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struct engine_mmio *mmio;
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u32 v;
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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restore_mocs(vgpu, ring_id);
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mmio = vgpu->gvt->engine_mmio_list;
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while (i915_mmio_reg_offset((mmio++)->reg)) {
|
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if (mmio->ring_id != ring_id)
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continue;
|
||||
|
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vgpu_vreg(vgpu, mmio->reg) = I915_READ_FW(mmio->reg);
|
||||
|
||||
if (mmio->mask) {
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vgpu_vreg(vgpu, mmio->reg) &= ~(mmio->mask << 16);
|
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v = mmio->value | (mmio->mask << 16);
|
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} else
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||||
v = mmio->value;
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||||
|
||||
if (mmio->in_context)
|
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continue;
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||||
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I915_WRITE_FW(mmio->reg, v);
|
||||
|
||||
trace_render_mmio(vgpu->id, "restore",
|
||||
i915_mmio_reg_offset(mmio->reg),
|
||||
mmio->value, v);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* intel_gvt_switch_render_mmio - switch mmio context of specific engine
|
||||
* @pre: the last vGPU that own the engine
|
||||
* @next: the vGPU to switch to
|
||||
* @ring_id: specify the engine
|
||||
*
|
||||
* If pre is null indicates that host own the engine. If next is null
|
||||
* indicates that we are switching to host workload.
|
||||
*/
|
||||
void intel_gvt_switch_mmio(struct intel_vgpu *pre,
|
||||
struct intel_vgpu *next, int ring_id)
|
||||
{
|
||||
struct drm_i915_private *dev_priv;
|
||||
|
||||
if (WARN_ON(!pre && !next))
|
||||
return;
|
||||
|
||||
gvt_dbg_render("switch ring %d from %s to %s\n", ring_id,
|
||||
pre ? "vGPU" : "host", next ? "vGPU" : "HOST");
|
||||
|
||||
dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv;
|
||||
|
||||
/**
|
||||
* We are using raw mmio access wrapper to improve the
|
||||
* performace for batch mmio read/write, so we need
|
||||
* handle forcewake mannually.
|
||||
*/
|
||||
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
|
||||
|
||||
/**
|
||||
* TODO: Optimize for vGPU to vGPU switch by merging
|
||||
* switch_mmio_to_host() and switch_mmio_to_vgpu().
|
||||
*/
|
||||
if (pre)
|
||||
switch_mmio_to_host(pre, ring_id);
|
||||
|
||||
if (next)
|
||||
switch_mmio_to_vgpu(next, ring_id);
|
||||
|
||||
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
|
||||
}
|
||||
|
||||
/**
|
||||
* intel_gvt_init_engine_mmio_context - Initiate the engine mmio list
|
||||
* @gvt: GVT device
|
||||
*
|
||||
*/
|
||||
void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt)
|
||||
{
|
||||
if (IS_SKYLAKE(gvt->dev_priv) || IS_KABYLAKE(gvt->dev_priv))
|
||||
gvt->engine_mmio_list = gen9_engine_mmio_list;
|
||||
else
|
||||
gvt->engine_mmio_list = gen8_engine_mmio_list;
|
||||
}
|
||||
Reference in New Issue
Block a user