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drm/msm/dp: enable SDP and SDE periph flush update

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DP controller can be setup to operate in either SDP update flush mode or
peripheral flush mode based on the DP controller hardware version.

Starting in DP v1.2, the hardware documents require the use of
peripheral flush mode for SDP packets such as PPS OR VSC SDP packets.

In-line with this guidance, lets program the DP controller to use
peripheral flush mode starting DP v1.2

Changes in v4:
	- Clear up that DP_MAINLINK_CTRL_FLUSH_MODE register requires
	  the use of bits [24:23]
	- Modify macros DP_MAINLINK_FLUSH_MODE_UPDATE_SDP and
	  DP_MAINLINK_FLUSH_MODE_SDP_PERIPH_UPDATE to explicitly set
	  their values in the bits of DP_MAINLINK_CTRL_FLUSH_MODE_MASK

Changes in v3:
	- Clear up that the DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE
	  macro is setting bits [24:23] to a value of 3

Changes in v2:
	- Use the original dp_catalog_hw_revision() function to
	  correctly check the DP HW version

Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/579621/
Link: https://lore.kernel.org/r/20240222194025.25329-16-quic_parellan@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
This commit is contained in:
Paloma Arellano
2024-02-22 11:40:00 -08:00
committed by Dmitry Baryshkov
parent 64f7b81f03
commit 21497a4633
4 changed files with 25 additions and 0 deletions
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17
drivers/gpu/drm/msm/dp/dp_catalog.c
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@@ -450,6 +450,23 @@ void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog,
dp_write_link(catalog, REG_DP_MISC1_MISC0, misc_val);
}
void dp_catalog_setup_peripheral_flush(struct dp_catalog *dp_catalog)
{
u32 mainlink_ctrl, hw_revision;
struct dp_catalog_private *catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
mainlink_ctrl = dp_read_link(catalog, REG_DP_MAINLINK_CTRL);
hw_revision = dp_catalog_hw_revision(dp_catalog);
if (hw_revision >= DP_HW_VERSION_1_2)
mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE;
else
mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_UPDATE_SDP;
dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
}
void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog,
u32 rate, u32 stream_rate_khz,
bool fixed_nvid, bool is_ycbcr_420)