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drm/amdgpu: add user fence context map v2

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This is a prerequisite for the GPU scheduler to make the order
of submission independent from the order of execution.

v2: properly implement the locking

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
This commit is contained in:
Christian König
2015-07-07 17:24:49 +02:00
committed by Alex Deucher
parent 91e1a5207e
commit 21c16bf634
4 changed files with 110 additions and 30 deletions
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4
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
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@@ -219,8 +219,10 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
/* wrap the last IB with fence */
if (ib->user) {
uint64_t addr = amdgpu_bo_gpu_offset(ib->user->bo);
ib->user->sequence = amdgpu_ctx_add_fence(ib->ctx, ring,
&ib->fence->base);
addr += ib->user->offset;
amdgpu_ring_emit_fence(ring, addr, ib->fence->seq,
amdgpu_ring_emit_fence(ring, addr, ib->user->sequence,
AMDGPU_FENCE_FLAG_64BIT);
}