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https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
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drm/msm: resync generated headers
resync to latest envytools db, fixes a typo: s/mpd4/mdp4/ Signed-off-by: Rob Clark <robdclark@gmail.com> Acked-by: David Brown <davidb@codeaurora.org>
This commit is contained in:
Rob Clark
@@ -4,16 +4,16 @@
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/* Autogenerated file, DO NOT EDIT manually!
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This file was generated by the rules-ng-ng headergen tool in this git repository:
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http://0x04.net/cgit/index.cgi/rules-ng-ng
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git clone git://0x04.net/rules-ng-ng
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http://github.com/freedreno/envytools/
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git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 30005 bytes, from 2013-07-19 21:30:48)
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- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 31003 bytes, from 2013-09-19 18:50:16)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9712 bytes, from 2013-05-26 15:22:37)
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- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51415 bytes, from 2013-08-03 14:26:05)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9759 bytes, from 2013-09-10 00:52:33)
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- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51983 bytes, from 2013-09-10 00:52:32)
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Copyright (C) 2013 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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@@ -637,11 +637,12 @@ static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
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#define REG_A3XX_GRAS_SU_MODE_CONTROL 0x00002070
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#define A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001
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#define A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002
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#define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007fc
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#define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 2
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static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(uint32_t val)
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#define A3XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004
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#define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8
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#define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3
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static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
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{
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return ((val) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
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return ((((uint32_t)(val * 4.0))) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
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}
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#define A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800
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@@ -745,6 +746,7 @@ static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val)
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}
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#define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00001000
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#define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM 0x00002000
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#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST 0x00400000
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#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK 0x07000000
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#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT 24
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static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
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@@ -767,7 +769,19 @@ static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val)
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return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK;
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}
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#define REG_A3XX_UNKNOWN_20C3 0x000020c3
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#define REG_A3XX_RB_ALPHA_REF 0x000020c3
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#define A3XX_RB_ALPHA_REF_UINT__MASK 0x0000ff00
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#define A3XX_RB_ALPHA_REF_UINT__SHIFT 8
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static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val)
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{
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return ((val) << A3XX_RB_ALPHA_REF_UINT__SHIFT) & A3XX_RB_ALPHA_REF_UINT__MASK;
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}
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#define A3XX_RB_ALPHA_REF_FLOAT__MASK 0xffff0000
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#define A3XX_RB_ALPHA_REF_FLOAT__SHIFT 16
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static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val)
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{
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return ((util_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK;
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}
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static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
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@@ -1002,7 +1016,7 @@ static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endi
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#define REG_A3XX_RB_DEPTH_CONTROL 0x00002100
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#define A3XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002
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#define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004
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#define A3XX_RB_DEPTH_CONTROL_EARLY_Z_ENABLE 0x00000008
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#define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00000008
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#define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070
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#define A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4
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static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
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@@ -1038,7 +1052,8 @@ static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val)
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#define REG_A3XX_RB_STENCIL_CONTROL 0x00002104
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#define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
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#define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000004
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#define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
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#define A3XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
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#define A3XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
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#define A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
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static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
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@@ -2074,6 +2089,7 @@ static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_op
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#define REG_A3XX_TP_PERFCOUNTER5_SELECT 0x00000f09
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#define REG_A3XX_TEX_SAMP_0 0x00000000
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#define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR 0x00000002
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#define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c
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#define A3XX_TEX_SAMP_0_XY_MAG__SHIFT 2
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static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val)
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@@ -2134,6 +2150,12 @@ static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val)
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{
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return ((val) << A3XX_TEX_CONST_0_SWIZ_W__SHIFT) & A3XX_TEX_CONST_0_SWIZ_W__MASK;
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}
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#define A3XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
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#define A3XX_TEX_CONST_0_MIPLVLS__SHIFT 16
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static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val)
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{
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return ((val) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT) & A3XX_TEX_CONST_0_MIPLVLS__MASK;
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}
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#define A3XX_TEX_CONST_0_FMT__MASK 0x1fc00000
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#define A3XX_TEX_CONST_0_FMT__SHIFT 22
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static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val)
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