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drm/amd/display: fix dcn3.1x mode validation on high bandwidth config
[why] 1. correct dram_channel_width (was hard coded to 4 for 32bit) 2. use dm's is_hvm_enable status flag for hostvm_en input for dml. 3. add a function to override to all dcn3.1x. Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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committed by
Alex Deucher
parent
5b8f9deaf3
commit
27142312c8
@@ -1648,7 +1648,7 @@ static int dcn315_populate_dml_pipes_from_context(
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const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB;
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DC_FP_START();
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dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
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dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
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DC_FP_END();
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for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
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@@ -1667,7 +1667,6 @@ static int dcn315_populate_dml_pipes_from_context(
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pipes[pipe_cnt].pipe.src.immediate_flip = true;
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pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
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pipes[pipe_cnt].pipe.src.gpuvm = true;
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pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
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pipes[pipe_cnt].pipe.src.dcc_rate = 3;
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pipes[pipe_cnt].dout.dsc_input_bpc = 0;
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