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Merge tag 'amd-drm-next-6.7-2023-10-13' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

Browse Source 
amd-drm-next-6.7-2023-10-13:

amdgpu:
- DC replay fixes
- Misc code cleanups and spelling fixes
- Documentation updates
- RAS EEPROM Updates
- FRU EEPROM Updates
- IP discovery updates
- SR-IOV fixes
- RAS updates
- DC PQ fixes
- SMU 13.0.6 updates
- GC 11.5 Support
- NBIO 7.11 Support
- GMC 11 Updates
- Reset fixes
- SMU 11.5 Updates
- SMU 13.0 OD support
- Use flexible arrays for bo list handling
- W=1 Fixes
- SubVP fixes
- DPIA fixes
- DCN 3.5 Support
- Devcoredump fixes
- VPE 6.1 support
- VCN 4.0 Updates
- S/G display fixes
- DML fixes
- DML2 Support
- MST fixes
- VRR fixes
- Enable seamless boot in more cases
- Enable content type property for HDMI
- OLED fixes
- Rework and clean up GPUVM TLB flushing
- DC ODM fixes
- DP 2.x fixes
- AGP aperture fixes
- SDMA firmware loading cleanups
- Cyan Skillfish GPU clock counter fix
- GC 11 GART fix
- Cache GPU fault info for userspace queries
- DC cursor check fixes
- eDP fixes
- DC FP handling fixes
- Variable sized array fixes
- SMU 13.0.x fixes
- IB start and size alignment fixes for VCN
- SMU 14 Support
- Suspend and resume sequence rework
- vkms fix

amdkfd:
- GC 11 fixes
- GC 10 fixes
- Doorbell fixes
- CWSR fixes
- SVM fixes
- Clean up GC info enumeration
- Rework memory limit handling
- Coherent memory handling fixes
- Use partial migrations in GPU faults
- TLB flush fixes
- DMA unmap fixes
- GC 9.4.3 fixes
- SQ interrupt fix
- GTT mapping fix
- GC 11.5 Support

radeon:
- Misc code cleanups
- W=1 Fixes
- Fix possible buffer overflow
- Fix possible NULL pointer dereference

UAPI:
- Add EXT_COHERENT memory allocation flags.  These allow for system scope atomics.
  Proposed userspace: https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface/pull/88
- Add support for new VPE engine.  This is a memory to memory copy engine with advanced scaling, CSC, and color management features
  Proposed mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25713
- Add INFO IOCTL interface to query GPU faults
  Proposed Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23238
  Proposed libdrm MR: https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/298

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231013175758.1735031-1-alexander.deucher@amd.com
This commit is contained in:
Dave Airlie
2023-10-18 16:08:07 +10:00
parent 0805725336 cd90511557
commit 27442758e9
569 changed files with 266191 additions and 5415 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/drm/amd/include/amd_shared.h
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@@ -83,6 +83,8 @@ enum amd_apu_flags {
* @AMD_IP_BLOCK_TYPE_VCN: Video Core/Codec Next
* @AMD_IP_BLOCK_TYPE_MES: Micro-Engine Scheduler
* @AMD_IP_BLOCK_TYPE_JPEG: JPEG Engine
* @AMD_IP_BLOCK_TYPE_VPE: Video Processing Engine
* @AMD_IP_BLOCK_TYPE_UMSCH_MM: User Mode Schduler for Multimedia
* @AMD_IP_BLOCK_TYPE_NUM: Total number of IP block types
*/
enum amd_ip_block_type {
@@ -100,6 +102,8 @@ enum amd_ip_block_type {
AMD_IP_BLOCK_TYPE_VCN,
AMD_IP_BLOCK_TYPE_MES,
AMD_IP_BLOCK_TYPE_JPEG,
AMD_IP_BLOCK_TYPE_VPE,
AMD_IP_BLOCK_TYPE_UMSCH_MM,
AMD_IP_BLOCK_TYPE_NUM,
};
@@ -297,6 +301,7 @@ struct amd_ip_funcs {
int (*hw_init)(void *handle);
int (*hw_fini)(void *handle);
void (*late_fini)(void *handle);
int (*prepare_suspend)(void *handle);
int (*suspend)(void *handle);
int (*resume)(void *handle);
bool (*is_idle)(void *handle);

15255
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_offset.h Normal file
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File diff suppressed because it is too large Load Diff

53412
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h Normal file
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File diff suppressed because it is too large Load Diff

10000
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h Normal file
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File diff suppressed because it is too large Load Diff

36531
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h Normal file
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File diff suppressed because it is too large Load Diff

1395
drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_3_0_offset.h Normal file
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File diff suppressed because it is too large Load Diff

6722
drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_3_3_0_sh_mask.h Normal file
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File diff suppressed because it is too large Load Diff

28
drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_6_sh_mask.h
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@@ -670,5 +670,33 @@
#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L
#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL
//MCMP1_IPIDT0
#define MCMP1_IPIDT0__InstanceIdLo__SHIFT 0x0
#define MCMP1_IPIDT0__HardwareID__SHIFT 0x20
#define MCMP1_IPIDT0__InstanceIdHi__SHIFT 0x2c
#define MCMP1_IPIDT0__McaType__SHIFT 0x30
#define MCMP1_IPIDT0__InstanceIdLo_MASK 0x00000000FFFFFFFFL
#define MCMP1_IPIDT0__HardwareID_MASK 0x00000FFF00000000L
#define MCMP1_IPIDT0__InstanceIdHi_MASK 0x0000F00000000000L
#define MCMP1_IPIDT0__McaType_MASK 0xFFFF000000000000L
//MCMP1_STATUST0
#define MCMP1_STATUST0__ErrorCode__SHIFT 0x0
#define MCMP1_STATUST0__ErrorCodeExt__SHIFT 0x10
#define MCMP1_STATUST0__PCC__SHIFT 0x39
#define MCMP1_STATUST0__UC__SHIFT 0x3d
#define MCMP1_STATUST0__Val__SHIFT 0x3f
#define MCMP1_STATUST0__ErrorCode_MASK 0x000000000000FFFFL
#define MCMP1_STATUST0__ErrorCodeExt_MASK 0x00000000003F0000L
#define MCMP1_STATUST0__PCC_MASK 0x0200000000000000L
#define MCMP1_STATUST0__UC_MASK 0x2000000000000000L
#define MCMP1_STATUST0__Val_MASK 0x8000000000000000L
//MCMP1_MISC0T0
#define MCMP1_MISC0T0__ErrCnt__SHIFT 0x20
#define MCMP1_MISC0T0__ErrCnt_MASK 0x00000FFF00000000L
#endif

359
drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_0_offset.h Normal file
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@@ -0,0 +1,359 @@
/*
* Copyright 2023 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*
*/
#ifndef _mp_14_0_0_OFFSET_HEADER
#define _mp_14_0_0_OFFSET_HEADER
// addressBlock: mp_SmuMp1_SmnDec
// base address: 0x0
#define regMP1_SMN_C2PMSG_0 0x0240
#define regMP1_SMN_C2PMSG_0_BASE_IDX 0
#define regMP1_SMN_C2PMSG_1 0x0241
#define regMP1_SMN_C2PMSG_1_BASE_IDX 0
#define regMP1_SMN_C2PMSG_2 0x0242
#define regMP1_SMN_C2PMSG_2_BASE_IDX 0
#define regMP1_SMN_C2PMSG_3 0x0243
#define regMP1_SMN_C2PMSG_3_BASE_IDX 0
#define regMP1_SMN_C2PMSG_4 0x0244
#define regMP1_SMN_C2PMSG_4_BASE_IDX 0
#define regMP1_SMN_C2PMSG_5 0x0245
#define regMP1_SMN_C2PMSG_5_BASE_IDX 0
#define regMP1_SMN_C2PMSG_6 0x0246
#define regMP1_SMN_C2PMSG_6_BASE_IDX 0
#define regMP1_SMN_C2PMSG_7 0x0247
#define regMP1_SMN_C2PMSG_7_BASE_IDX 0
#define regMP1_SMN_C2PMSG_8 0x0248
#define regMP1_SMN_C2PMSG_8_BASE_IDX 0
#define regMP1_SMN_C2PMSG_9 0x0249
#define regMP1_SMN_C2PMSG_9_BASE_IDX 0
#define regMP1_SMN_C2PMSG_10 0x024a
#define regMP1_SMN_C2PMSG_10_BASE_IDX 0
#define regMP1_SMN_C2PMSG_11 0x024b
#define regMP1_SMN_C2PMSG_11_BASE_IDX 0
#define regMP1_SMN_C2PMSG_12 0x024c
#define regMP1_SMN_C2PMSG_12_BASE_IDX 0
#define regMP1_SMN_C2PMSG_13 0x024d
#define regMP1_SMN_C2PMSG_13_BASE_IDX 0
#define regMP1_SMN_C2PMSG_14 0x024e
#define regMP1_SMN_C2PMSG_14_BASE_IDX 0
#define regMP1_SMN_C2PMSG_15 0x024f
#define regMP1_SMN_C2PMSG_15_BASE_IDX 0
#define regMP1_SMN_C2PMSG_16 0x0250
#define regMP1_SMN_C2PMSG_16_BASE_IDX 0
#define regMP1_SMN_C2PMSG_17 0x0251
#define regMP1_SMN_C2PMSG_17_BASE_IDX 0
#define regMP1_SMN_C2PMSG_18 0x0252
#define regMP1_SMN_C2PMSG_18_BASE_IDX 0
#define regMP1_SMN_C2PMSG_19 0x0253
#define regMP1_SMN_C2PMSG_19_BASE_IDX 0
#define regMP1_SMN_C2PMSG_20 0x0254
#define regMP1_SMN_C2PMSG_20_BASE_IDX 0
#define regMP1_SMN_C2PMSG_21 0x0255
#define regMP1_SMN_C2PMSG_21_BASE_IDX 0
#define regMP1_SMN_C2PMSG_22 0x0256
#define regMP1_SMN_C2PMSG_22_BASE_IDX 0
#define regMP1_SMN_C2PMSG_23 0x0257
#define regMP1_SMN_C2PMSG_23_BASE_IDX 0
#define regMP1_SMN_C2PMSG_24 0x0258
#define regMP1_SMN_C2PMSG_24_BASE_IDX 0
#define regMP1_SMN_C2PMSG_25 0x0259
#define regMP1_SMN_C2PMSG_25_BASE_IDX 0
#define regMP1_SMN_C2PMSG_26 0x025a
#define regMP1_SMN_C2PMSG_26_BASE_IDX 0
#define regMP1_SMN_C2PMSG_27 0x025b
#define regMP1_SMN_C2PMSG_27_BASE_IDX 0
#define regMP1_SMN_C2PMSG_28 0x025c
#define regMP1_SMN_C2PMSG_28_BASE_IDX 0
#define regMP1_SMN_C2PMSG_29 0x025d
#define regMP1_SMN_C2PMSG_29_BASE_IDX 0
#define regMP1_SMN_C2PMSG_30 0x025e
#define regMP1_SMN_C2PMSG_30_BASE_IDX 0
#define regMP1_SMN_C2PMSG_31 0x025f
#define regMP1_SMN_C2PMSG_31_BASE_IDX 0
#define regMP1_SMN_C2PMSG_32 0x0260
#define regMP1_SMN_C2PMSG_32_BASE_IDX 0
#define regMP1_SMN_C2PMSG_33 0x0261
#define regMP1_SMN_C2PMSG_33_BASE_IDX 0
#define regMP1_SMN_C2PMSG_34 0x0262
#define regMP1_SMN_C2PMSG_34_BASE_IDX 0
#define regMP1_SMN_C2PMSG_35 0x0263
#define regMP1_SMN_C2PMSG_35_BASE_IDX 0
#define regMP1_SMN_C2PMSG_36 0x0264
#define regMP1_SMN_C2PMSG_36_BASE_IDX 0
#define regMP1_SMN_C2PMSG_37 0x0265
#define regMP1_SMN_C2PMSG_37_BASE_IDX 0
#define regMP1_SMN_C2PMSG_38 0x0266
#define regMP1_SMN_C2PMSG_38_BASE_IDX 0
#define regMP1_SMN_C2PMSG_39 0x0267
#define regMP1_SMN_C2PMSG_39_BASE_IDX 0
#define regMP1_SMN_C2PMSG_40 0x0268
#define regMP1_SMN_C2PMSG_40_BASE_IDX 0
#define regMP1_SMN_C2PMSG_41 0x0269
#define regMP1_SMN_C2PMSG_41_BASE_IDX 0
#define regMP1_SMN_C2PMSG_42 0x026a
#define regMP1_SMN_C2PMSG_42_BASE_IDX 0
#define regMP1_SMN_C2PMSG_43 0x026b
#define regMP1_SMN_C2PMSG_43_BASE_IDX 0
#define regMP1_SMN_C2PMSG_44 0x026c
#define regMP1_SMN_C2PMSG_44_BASE_IDX 0
#define regMP1_SMN_C2PMSG_45 0x026d
#define regMP1_SMN_C2PMSG_45_BASE_IDX 0
#define regMP1_SMN_C2PMSG_46 0x026e
#define regMP1_SMN_C2PMSG_46_BASE_IDX 0
#define regMP1_SMN_C2PMSG_47 0x026f
#define regMP1_SMN_C2PMSG_47_BASE_IDX 0
#define regMP1_SMN_C2PMSG_48 0x0270
#define regMP1_SMN_C2PMSG_48_BASE_IDX 0
#define regMP1_SMN_C2PMSG_49 0x0271
#define regMP1_SMN_C2PMSG_49_BASE_IDX 0
#define regMP1_SMN_C2PMSG_50 0x0272
#define regMP1_SMN_C2PMSG_50_BASE_IDX 0
#define regMP1_SMN_C2PMSG_51 0x0273
#define regMP1_SMN_C2PMSG_51_BASE_IDX 0
#define regMP1_SMN_C2PMSG_52 0x0274
#define regMP1_SMN_C2PMSG_52_BASE_IDX 0
#define regMP1_SMN_C2PMSG_53 0x0275
#define regMP1_SMN_C2PMSG_53_BASE_IDX 0
#define regMP1_SMN_C2PMSG_54 0x0276
#define regMP1_SMN_C2PMSG_54_BASE_IDX 0
#define regMP1_SMN_C2PMSG_55 0x0277
#define regMP1_SMN_C2PMSG_55_BASE_IDX 0
#define regMP1_SMN_C2PMSG_56 0x0278
#define regMP1_SMN_C2PMSG_56_BASE_IDX 0
#define regMP1_SMN_C2PMSG_57 0x0279
#define regMP1_SMN_C2PMSG_57_BASE_IDX 0
#define regMP1_SMN_C2PMSG_58 0x027a
#define regMP1_SMN_C2PMSG_58_BASE_IDX 0
#define regMP1_SMN_C2PMSG_59 0x027b
#define regMP1_SMN_C2PMSG_59_BASE_IDX 0
#define regMP1_SMN_C2PMSG_60 0x027c
#define regMP1_SMN_C2PMSG_60_BASE_IDX 0
#define regMP1_SMN_C2PMSG_61 0x027d
#define regMP1_SMN_C2PMSG_61_BASE_IDX 0
#define regMP1_SMN_C2PMSG_62 0x027e
#define regMP1_SMN_C2PMSG_62_BASE_IDX 0
#define regMP1_SMN_C2PMSG_63 0x027f
#define regMP1_SMN_C2PMSG_63_BASE_IDX 0
#define regMP1_SMN_C2PMSG_64 0x0280
#define regMP1_SMN_C2PMSG_64_BASE_IDX 0
#define regMP1_SMN_C2PMSG_65 0x0281
#define regMP1_SMN_C2PMSG_65_BASE_IDX 0
#define regMP1_SMN_C2PMSG_66 0x0282
#define regMP1_SMN_C2PMSG_66_BASE_IDX 0
#define regMP1_SMN_C2PMSG_67 0x0283
#define regMP1_SMN_C2PMSG_67_BASE_IDX 0
#define regMP1_SMN_C2PMSG_68 0x0284
#define regMP1_SMN_C2PMSG_68_BASE_IDX 0
#define regMP1_SMN_C2PMSG_69 0x0285
#define regMP1_SMN_C2PMSG_69_BASE_IDX 0
#define regMP1_SMN_C2PMSG_70 0x0286
#define regMP1_SMN_C2PMSG_70_BASE_IDX 0
#define regMP1_SMN_C2PMSG_71 0x0287
#define regMP1_SMN_C2PMSG_71_BASE_IDX 0
#define regMP1_SMN_C2PMSG_72 0x0288
#define regMP1_SMN_C2PMSG_72_BASE_IDX 0
#define regMP1_SMN_C2PMSG_73 0x0289
#define regMP1_SMN_C2PMSG_73_BASE_IDX 0
#define regMP1_SMN_C2PMSG_74 0x028a
#define regMP1_SMN_C2PMSG_74_BASE_IDX 0
#define regMP1_SMN_C2PMSG_75 0x028b
#define regMP1_SMN_C2PMSG_75_BASE_IDX 0
#define regMP1_SMN_C2PMSG_76 0x028c
#define regMP1_SMN_C2PMSG_76_BASE_IDX 0
#define regMP1_SMN_C2PMSG_77 0x028d
#define regMP1_SMN_C2PMSG_77_BASE_IDX 0
#define regMP1_SMN_C2PMSG_78 0x028e
#define regMP1_SMN_C2PMSG_78_BASE_IDX 0
#define regMP1_SMN_C2PMSG_79 0x028f
#define regMP1_SMN_C2PMSG_79_BASE_IDX 0
#define regMP1_SMN_C2PMSG_80 0x0290
#define regMP1_SMN_C2PMSG_80_BASE_IDX 0
#define regMP1_SMN_C2PMSG_81 0x0291
#define regMP1_SMN_C2PMSG_81_BASE_IDX 0
#define regMP1_SMN_C2PMSG_82 0x0292
#define regMP1_SMN_C2PMSG_82_BASE_IDX 0
#define regMP1_SMN_C2PMSG_83 0x0293
#define regMP1_SMN_C2PMSG_83_BASE_IDX 0
#define regMP1_SMN_C2PMSG_84 0x0294
#define regMP1_SMN_C2PMSG_84_BASE_IDX 0
#define regMP1_SMN_C2PMSG_85 0x0295
#define regMP1_SMN_C2PMSG_85_BASE_IDX 0
#define regMP1_SMN_C2PMSG_86 0x0296
#define regMP1_SMN_C2PMSG_86_BASE_IDX 0
#define regMP1_SMN_C2PMSG_87 0x0297
#define regMP1_SMN_C2PMSG_87_BASE_IDX 0
#define regMP1_SMN_C2PMSG_88 0x0298
#define regMP1_SMN_C2PMSG_88_BASE_IDX 0
#define regMP1_SMN_C2PMSG_89 0x0299
#define regMP1_SMN_C2PMSG_89_BASE_IDX 0
#define regMP1_SMN_C2PMSG_90 0x029a
#define regMP1_SMN_C2PMSG_90_BASE_IDX 0
#define regMP1_SMN_C2PMSG_91 0x029b
#define regMP1_SMN_C2PMSG_91_BASE_IDX 0
#define regMP1_SMN_C2PMSG_92 0x029c
#define regMP1_SMN_C2PMSG_92_BASE_IDX 0
#define regMP1_SMN_C2PMSG_93 0x029d
#define regMP1_SMN_C2PMSG_93_BASE_IDX 0
#define regMP1_SMN_C2PMSG_94 0x029e
#define regMP1_SMN_C2PMSG_94_BASE_IDX 0
#define regMP1_SMN_C2PMSG_95 0x029f
#define regMP1_SMN_C2PMSG_95_BASE_IDX 0
#define regMP1_SMN_C2PMSG_96 0x02a0
#define regMP1_SMN_C2PMSG_96_BASE_IDX 0
#define regMP1_SMN_C2PMSG_97 0x02a1
#define regMP1_SMN_C2PMSG_97_BASE_IDX 0
#define regMP1_SMN_C2PMSG_98 0x02a2
#define regMP1_SMN_C2PMSG_98_BASE_IDX 0
#define regMP1_SMN_C2PMSG_99 0x02a3
#define regMP1_SMN_C2PMSG_99_BASE_IDX 0
#define regMP1_SMN_C2PMSG_100 0x02a4
#define regMP1_SMN_C2PMSG_100_BASE_IDX 0
#define regMP1_SMN_C2PMSG_101 0x02a5
#define regMP1_SMN_C2PMSG_101_BASE_IDX 0
#define regMP1_SMN_C2PMSG_102 0x02a6
#define regMP1_SMN_C2PMSG_102_BASE_IDX 0
#define regMP1_SMN_C2PMSG_103 0x02a7
#define regMP1_SMN_C2PMSG_103_BASE_IDX 0
#define regMP1_SMN_C2PMSG_104 0x02a8
#define regMP1_SMN_C2PMSG_104_BASE_IDX 0
#define regMP1_SMN_C2PMSG_105 0x02a9
#define regMP1_SMN_C2PMSG_105_BASE_IDX 0
#define regMP1_SMN_C2PMSG_106 0x02aa
#define regMP1_SMN_C2PMSG_106_BASE_IDX 0
#define regMP1_SMN_C2PMSG_107 0x02ab
#define regMP1_SMN_C2PMSG_107_BASE_IDX 0
#define regMP1_SMN_C2PMSG_108 0x02ac
#define regMP1_SMN_C2PMSG_108_BASE_IDX 0
#define regMP1_SMN_C2PMSG_109 0x02ad
#define regMP1_SMN_C2PMSG_109_BASE_IDX 0
#define regMP1_SMN_C2PMSG_110 0x02ae
#define regMP1_SMN_C2PMSG_110_BASE_IDX 0
#define regMP1_SMN_C2PMSG_111 0x02af
#define regMP1_SMN_C2PMSG_111_BASE_IDX 0
#define regMP1_SMN_C2PMSG_112 0x02b0
#define regMP1_SMN_C2PMSG_112_BASE_IDX 0
#define regMP1_SMN_C2PMSG_113 0x02b1
#define regMP1_SMN_C2PMSG_113_BASE_IDX 0
#define regMP1_SMN_C2PMSG_114 0x02b2
#define regMP1_SMN_C2PMSG_114_BASE_IDX 0
#define regMP1_SMN_C2PMSG_115 0x02b3
#define regMP1_SMN_C2PMSG_115_BASE_IDX 0
#define regMP1_SMN_C2PMSG_116 0x02b4
#define regMP1_SMN_C2PMSG_116_BASE_IDX 0
#define regMP1_SMN_C2PMSG_117 0x02b5
#define regMP1_SMN_C2PMSG_117_BASE_IDX 0
#define regMP1_SMN_C2PMSG_118 0x02b6
#define regMP1_SMN_C2PMSG_118_BASE_IDX 0
#define regMP1_SMN_C2PMSG_119 0x02b7
#define regMP1_SMN_C2PMSG_119_BASE_IDX 0
#define regMP1_SMN_C2PMSG_120 0x02b8
#define regMP1_SMN_C2PMSG_120_BASE_IDX 0
#define regMP1_SMN_C2PMSG_121 0x02b9
#define regMP1_SMN_C2PMSG_121_BASE_IDX 0
#define regMP1_SMN_C2PMSG_122 0x02ba
#define regMP1_SMN_C2PMSG_122_BASE_IDX 0
#define regMP1_SMN_C2PMSG_123 0x02bb
#define regMP1_SMN_C2PMSG_123_BASE_IDX 0
#define regMP1_SMN_C2PMSG_124 0x02bc
#define regMP1_SMN_C2PMSG_124_BASE_IDX 0
#define regMP1_SMN_C2PMSG_125 0x02bd
#define regMP1_SMN_C2PMSG_125_BASE_IDX 0
#define regMP1_SMN_C2PMSG_126 0x02be
#define regMP1_SMN_C2PMSG_126_BASE_IDX 0
#define regMP1_SMN_C2PMSG_127 0x02bf
#define regMP1_SMN_C2PMSG_127_BASE_IDX 0
#define regMP1_SMN_IH_CREDIT 0x0340
#define regMP1_SMN_IH_CREDIT_BASE_IDX 0
#define regMP1_SMN_IH_SW_INT 0x0341
#define regMP1_SMN_IH_SW_INT_BASE_IDX 0
#define regMP1_SMN_IH_SW_INT_CTRL 0x0342
#define regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0
#define regMP1_SMN_FPS_CNT 0x0343
#define regMP1_SMN_FPS_CNT_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH0 0x03c0
#define regMP1_SMN_EXT_SCRATCH0_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH1 0x03c1
#define regMP1_SMN_EXT_SCRATCH1_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH2 0x03c2
#define regMP1_SMN_EXT_SCRATCH2_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH3 0x03c3
#define regMP1_SMN_EXT_SCRATCH3_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH4 0x03c4
#define regMP1_SMN_EXT_SCRATCH4_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH5 0x03c5
#define regMP1_SMN_EXT_SCRATCH5_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH6 0x03c6
#define regMP1_SMN_EXT_SCRATCH6_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH7 0x03c7
#define regMP1_SMN_EXT_SCRATCH7_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH8 0x03c8
#define regMP1_SMN_EXT_SCRATCH8_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH9 0x03c9
#define regMP1_SMN_EXT_SCRATCH9_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH10 0x03ca
#define regMP1_SMN_EXT_SCRATCH10_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH11 0x03cb
#define regMP1_SMN_EXT_SCRATCH11_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH12 0x03cc
#define regMP1_SMN_EXT_SCRATCH12_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH13 0x03cd
#define regMP1_SMN_EXT_SCRATCH13_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH14 0x03ce
#define regMP1_SMN_EXT_SCRATCH14_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH15 0x03cf
#define regMP1_SMN_EXT_SCRATCH15_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH16 0x03d0
#define regMP1_SMN_EXT_SCRATCH16_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH17 0x03d1
#define regMP1_SMN_EXT_SCRATCH17_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH18 0x03d2
#define regMP1_SMN_EXT_SCRATCH18_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH19 0x03d3
#define regMP1_SMN_EXT_SCRATCH19_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH20 0x03d4
#define regMP1_SMN_EXT_SCRATCH20_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH21 0x03d5
#define regMP1_SMN_EXT_SCRATCH21_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH22 0x03d6
#define regMP1_SMN_EXT_SCRATCH22_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH23 0x03d7
#define regMP1_SMN_EXT_SCRATCH23_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH24 0x03d8
#define regMP1_SMN_EXT_SCRATCH24_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH25 0x03d9
#define regMP1_SMN_EXT_SCRATCH25_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH26 0x03da
#define regMP1_SMN_EXT_SCRATCH26_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH27 0x03db
#define regMP1_SMN_EXT_SCRATCH27_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH28 0x03dc
#define regMP1_SMN_EXT_SCRATCH28_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH29 0x03dd
#define regMP1_SMN_EXT_SCRATCH29_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH30 0x03de
#define regMP1_SMN_EXT_SCRATCH30_BASE_IDX 0
#define regMP1_SMN_EXT_SCRATCH31 0x03df
#define regMP1_SMN_EXT_SCRATCH31_BASE_IDX 0
#endif

534
drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_0_sh_mask.h Normal file
View File

@@ -0,0 +1,534 @@
/*
* Copyright 2023 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef _mp_14_0_0_SH_MASK_HEADER
#define _mp_14_0_0_SH_MASK_HEADER
// addressBlock: mp_SmuMp1Pub_CruDec
//MP1_CRU1_MP1_FIRMWARE_FLAGS
#define MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
#define MP1_CRU1_MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
#define MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L
#define MP1_CRU1_MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL
// addressBlock: mp_SmuMp1_SmnDec
//MP1_SMN_C2PMSG_0
#define MP1_SMN_C2PMSG_0__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_1
#define MP1_SMN_C2PMSG_1__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_2
#define MP1_SMN_C2PMSG_2__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_3
#define MP1_SMN_C2PMSG_3__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_4
#define MP1_SMN_C2PMSG_4__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_5
#define MP1_SMN_C2PMSG_5__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_6
#define MP1_SMN_C2PMSG_6__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_7
#define MP1_SMN_C2PMSG_7__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_8
#define MP1_SMN_C2PMSG_8__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_9
#define MP1_SMN_C2PMSG_9__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_10
#define MP1_SMN_C2PMSG_10__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_11
#define MP1_SMN_C2PMSG_11__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_12
#define MP1_SMN_C2PMSG_12__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_13
#define MP1_SMN_C2PMSG_13__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_14
#define MP1_SMN_C2PMSG_14__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_15
#define MP1_SMN_C2PMSG_15__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_16
#define MP1_SMN_C2PMSG_16__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_17
#define MP1_SMN_C2PMSG_17__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_18
#define MP1_SMN_C2PMSG_18__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_19
#define MP1_SMN_C2PMSG_19__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_20
#define MP1_SMN_C2PMSG_20__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_21
#define MP1_SMN_C2PMSG_21__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_22
#define MP1_SMN_C2PMSG_22__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_23
#define MP1_SMN_C2PMSG_23__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_24
#define MP1_SMN_C2PMSG_24__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_25
#define MP1_SMN_C2PMSG_25__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_26
#define MP1_SMN_C2PMSG_26__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_27
#define MP1_SMN_C2PMSG_27__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_28
#define MP1_SMN_C2PMSG_28__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_29
#define MP1_SMN_C2PMSG_29__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_30
#define MP1_SMN_C2PMSG_30__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_31
#define MP1_SMN_C2PMSG_31__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_32
#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_33
#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_34
#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_35
#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_36
#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_37
#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_38
#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_39
#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_40
#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_41
#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_42
#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_43
#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_44
#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_45
#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_46
#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_47
#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_48
#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_49
#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_50
#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_51
#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_52
#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_53
#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_54
#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_55
#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_56
#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_57
#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_58
#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_59
#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_60
#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_61
#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_62
#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_63
#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_64
#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_65
#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_66
#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_67
#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_68
#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_69
#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_70
#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_71
#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_72
#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_73
#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_74
#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_75
#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_76
#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_77
#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_78
#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_79
#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_80
#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_81
#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_82
#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_83
#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_84
#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_85
#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_86
#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_87
#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_88
#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_89
#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_90
#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_91
#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_92
#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_93
#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_94
#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_95
#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_96
#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_97
#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_98
#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_99
#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_100
#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_101
#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_102
#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_103
#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_104
#define MP1_SMN_C2PMSG_104__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_104__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_105
#define MP1_SMN_C2PMSG_105__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_105__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_106
#define MP1_SMN_C2PMSG_106__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_106__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_107
#define MP1_SMN_C2PMSG_107__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_107__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_108
#define MP1_SMN_C2PMSG_108__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_108__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_109
#define MP1_SMN_C2PMSG_109__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_109__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_110
#define MP1_SMN_C2PMSG_110__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_110__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_111
#define MP1_SMN_C2PMSG_111__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_111__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_112
#define MP1_SMN_C2PMSG_112__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_112__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_113
#define MP1_SMN_C2PMSG_113__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_113__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_114
#define MP1_SMN_C2PMSG_114__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_114__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_115
#define MP1_SMN_C2PMSG_115__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_115__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_116
#define MP1_SMN_C2PMSG_116__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_116__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_117
#define MP1_SMN_C2PMSG_117__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_117__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_118
#define MP1_SMN_C2PMSG_118__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_118__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_119
#define MP1_SMN_C2PMSG_119__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_119__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_120
#define MP1_SMN_C2PMSG_120__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_120__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_121
#define MP1_SMN_C2PMSG_121__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_121__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_122
#define MP1_SMN_C2PMSG_122__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_122__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_123
#define MP1_SMN_C2PMSG_123__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_123__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_124
#define MP1_SMN_C2PMSG_124__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_124__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_125
#define MP1_SMN_C2PMSG_125__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_125__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_126
#define MP1_SMN_C2PMSG_126__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_126__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_C2PMSG_127
#define MP1_SMN_C2PMSG_127__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_127__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_IH_CREDIT
#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L
//MP1_SMN_IH_SW_INT
#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0
#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8
#define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL
#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L
//MP1_SMN_IH_SW_INT_CTRL
#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0
#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8
#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L
#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L
//MP1_SMN_FPS_CNT
#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0
#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH0
#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH1
#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH2
#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH3
#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH4
#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH5
#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH6
#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH7
#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH8
#define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH8__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH9
#define MP1_SMN_EXT_SCRATCH9__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH9__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH10
#define MP1_SMN_EXT_SCRATCH10__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH10__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH11
#define MP1_SMN_EXT_SCRATCH11__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH11__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH12
#define MP1_SMN_EXT_SCRATCH12__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH12__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH13
#define MP1_SMN_EXT_SCRATCH13__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH13__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH14
#define MP1_SMN_EXT_SCRATCH14__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH14__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH15
#define MP1_SMN_EXT_SCRATCH15__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH15__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH16
#define MP1_SMN_EXT_SCRATCH16__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH16__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH17
#define MP1_SMN_EXT_SCRATCH17__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH17__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH18
#define MP1_SMN_EXT_SCRATCH18__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH18__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH19
#define MP1_SMN_EXT_SCRATCH19__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH19__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH20
#define MP1_SMN_EXT_SCRATCH20__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH20__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH21
#define MP1_SMN_EXT_SCRATCH21__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH21__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH22
#define MP1_SMN_EXT_SCRATCH22__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH22__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH23
#define MP1_SMN_EXT_SCRATCH23__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH23__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH24
#define MP1_SMN_EXT_SCRATCH24__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH24__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH25
#define MP1_SMN_EXT_SCRATCH25__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH25__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH26
#define MP1_SMN_EXT_SCRATCH26__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH26__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH27
#define MP1_SMN_EXT_SCRATCH27__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH27__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH28
#define MP1_SMN_EXT_SCRATCH28__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH28__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH29
#define MP1_SMN_EXT_SCRATCH29__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH29__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH30
#define MP1_SMN_EXT_SCRATCH30__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH30__DATA_MASK 0xFFFFFFFFL
//MP1_SMN_EXT_SCRATCH31
#define MP1_SMN_EXT_SCRATCH31__DATA__SHIFT 0x0
#define MP1_SMN_EXT_SCRATCH31__DATA_MASK 0xFFFFFFFFL
#endif

9394
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h Normal file
View File

File diff suppressed because it is too large Load Diff

57846
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h Normal file
View File

File diff suppressed because it is too large Load Diff

33
drivers/gpu/drm/amd/include/asic_reg/umc/umc_12_0_0_offset.h Normal file
View File

@@ -0,0 +1,33 @@
/*
* Copyright (C) 2023 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _umc_12_0_0_OFFSET_HEADER
#define _umc_12_0_0_OFFSET_HEADER
#define regUMCCH0_OdEccCntSel 0x032c
#define regUMCCH0_OdEccCntSel_BASE_IDX 0
#define regUMCCH0_OdEccErrCnt 0x032d
#define regUMCCH0_OdEccErrCnt_BASE_IDX 0
#define regMCA_UMC_UMC0_MCUMC_STATUST0 0x03c2
#define regMCA_UMC_UMC0_MCUMC_STATUST0_BASE_IDX 0
#define regMCA_UMC_UMC0_MCUMC_ADDRT0 0x03c4
#define regMCA_UMC_UMC0_MCUMC_ADDRT0_BASE_IDX 0
#endif

95
drivers/gpu/drm/amd/include/asic_reg/umc/umc_12_0_0_sh_mask.h Normal file
View File

@@ -0,0 +1,95 @@
/*
* Copyright (C) 2023 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _umc_12_0_0_SH_MASK_HEADER
#define _umc_12_0_0_SH_MASK_HEADER
//UMCCH0_OdEccCntSel
#define UMCCH0_OdEccCntSel__OdEccCntSel__SHIFT 0x0
#define UMCCH0_OdEccCntSel__OdEccErrInt__SHIFT 0x4
#define UMCCH0_OdEccCntSel__OdEccCntSel_MASK 0x00000007L
#define UMCCH0_OdEccCntSel__OdEccErrInt_MASK 0x00000030L
//UMCCH0_OdEccErrCnt
#define UMCCH0_OdEccErrCnt__Cnt__SHIFT 0x0
#define UMCCH0_OdEccErrCnt__CntOvr__SHIFT 0x10
#define UMCCH0_OdEccErrCnt__OvrClr__SHIFT 0x11
#define UMCCH0_OdEccErrCnt__Cnt_MASK 0x0000FFFFL
#define UMCCH0_OdEccErrCnt__CntOvr_MASK 0x00010000L
#define UMCCH0_OdEccErrCnt__OvrClr_MASK 0x00020000L
//MCA_UMC_UMC0_MCUMC_STATUST0
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode__SHIFT 0x0
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt__SHIFT 0x10
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV22__SHIFT 0x16
#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrLsb__SHIFT 0x18
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV30__SHIFT 0x1e
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId__SHIFT 0x20
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV38__SHIFT 0x26
#define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub__SHIFT 0x28
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV41__SHIFT 0x29
#define MCA_UMC_UMC0_MCUMC_STATUST0__Poison__SHIFT 0x2b
#define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred__SHIFT 0x2c
#define MCA_UMC_UMC0_MCUMC_STATUST0__UECC__SHIFT 0x2d
#define MCA_UMC_UMC0_MCUMC_STATUST0__CECC__SHIFT 0x2e
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV47__SHIFT 0x2f
#define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent__SHIFT 0x34
#define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV__SHIFT 0x35
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV54__SHIFT 0x36
#define MCA_UMC_UMC0_MCUMC_STATUST0__TCC__SHIFT 0x37
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal__SHIFT 0x38
#define MCA_UMC_UMC0_MCUMC_STATUST0__PCC__SHIFT 0x39
#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV__SHIFT 0x3a
#define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV__SHIFT 0x3b
#define MCA_UMC_UMC0_MCUMC_STATUST0__En__SHIFT 0x3c
#define MCA_UMC_UMC0_MCUMC_STATUST0__UC__SHIFT 0x3d
#define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow__SHIFT 0x3e
#define MCA_UMC_UMC0_MCUMC_STATUST0__Val__SHIFT 0x3f
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCode_MASK 0x000000000000FFFFL
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrorCodeExt_MASK 0x00000000003F0000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV22_MASK 0x0000000000C00000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrLsb_MASK 0x000000003F000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV30_MASK 0x00000000C0000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreId_MASK 0x0000003F00000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV38_MASK 0x000000C000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Scrub_MASK 0x0000010000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV41_MASK 0x0000060000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Poison_MASK 0x0000080000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Deferred_MASK 0x0000100000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__UECC_MASK 0x0000200000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__CECC_MASK 0x0000400000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV47_MASK 0x000F800000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Transparent_MASK 0x0010000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__SyndV_MASK 0x0020000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__RESERV54_MASK 0x0040000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__TCC_MASK 0x0080000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__ErrCoreIdVal_MASK 0x0100000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__PCC_MASK 0x0200000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__AddrV_MASK 0x0400000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__MiscV_MASK 0x0800000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__En_MASK 0x1000000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__UC_MASK 0x2000000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Overflow_MASK 0x4000000000000000L
#define MCA_UMC_UMC0_MCUMC_STATUST0__Val_MASK 0x8000000000000000L
//MCA_UMC_UMC0_MCUMC_ADDRT0
#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr__SHIFT 0x0
#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved__SHIFT 0x38
#define MCA_UMC_UMC0_MCUMC_ADDRT0__ErrorAddr_MASK 0x00FFFFFFFFFFFFFFL
#define MCA_UMC_UMC0_MCUMC_ADDRT0__Reserved_MASK 0xFF00000000000000L
#endif

422
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_offset.h
View File

@@ -1305,6 +1305,32 @@
#define regVCN_RB3_DB_CTRL_BASE_IDX 1
#define regVCN_RB4_DB_CTRL 0x0075
#define regVCN_RB4_DB_CTRL_BASE_IDX 1
#define regVCN_UMSCH_RB_DB_CTRL 0x0076
#define regVCN_UMSCH_RB_DB_CTRL_BASE_IDX 1
#define regVCN_AGDB_CTRL0 0x0079
#define regVCN_AGDB_CTRL0_BASE_IDX 1
#define regVCN_AGDB_CTRL1 0x007a
#define regVCN_AGDB_CTRL1_BASE_IDX 1
#define regVCN_AGDB_CTRL2 0x007b
#define regVCN_AGDB_CTRL2_BASE_IDX 1
#define regVCN_AGDB_CTRL3 0x007c
#define regVCN_AGDB_CTRL3_BASE_IDX 1
#define regVCN_AGDB_CTRL4 0x007d
#define regVCN_AGDB_CTRL4_BASE_IDX 1
#define regVCN_AGDB_CTRL5 0x007e
#define regVCN_AGDB_CTRL5_BASE_IDX 1
#define regVCN_AGDB_MASK0 0x007f
#define regVCN_AGDB_MASK0_BASE_IDX 1
#define regVCN_AGDB_MASK1 0x0080
#define regVCN_AGDB_MASK1_BASE_IDX 1
#define regVCN_AGDB_MASK2 0x0081
#define regVCN_AGDB_MASK2_BASE_IDX 1
#define regVCN_AGDB_MASK3 0x0082
#define regVCN_AGDB_MASK3_BASE_IDX 1
#define regVCN_AGDB_MASK4 0x0083
#define regVCN_AGDB_MASK4_BASE_IDX 1
#define regVCN_AGDB_MASK5 0x0084
#define regVCN_AGDB_MASK5_BASE_IDX 1
#define regVCN_RB_ENABLE 0x0085
#define regVCN_RB_ENABLE_BASE_IDX 1
#define regVCN_RB_WPTR_CTRL 0x0086
@@ -1556,6 +1582,402 @@
#define regVCN_RAS_CNTL_MMSCH 0x0914
#define regVCN_RAS_CNTL_MMSCH_BASE_IDX 1
#define regVCN_UMSCH_MES_UTCL1_CNTL 0x0759
#define regVCN_UMSCH_MES_UTCL1_CNTL_BASE_IDX 1
#define regVCN_UMSCH_MES_BUSY 0x075a
#define regVCN_UMSCH_MES_BUSY_BASE_IDX 1
#define regVCN_UMSCH_RB_BASE_LO 0x075b
#define regVCN_UMSCH_RB_BASE_LO_BASE_IDX 1
#define regVCN_UMSCH_RB_BASE_HI 0x075c
#define regVCN_UMSCH_RB_BASE_HI_BASE_IDX 1
#define regVCN_UMSCH_RB_SIZE 0x075d
#define regVCN_UMSCH_RB_SIZE_BASE_IDX 1
#define regVCN_UMSCH_RB_RPTR 0x075e
#define regVCN_UMSCH_RB_RPTR_BASE_IDX 1
#define regVCN_UMSCH_RB_WPTR 0x075f
#define regVCN_UMSCH_RB_WPTR_BASE_IDX 1
#define regVCN_UMSCH_MASTINT_EN 0x0760
#define regVCN_UMSCH_MASTINT_EN_BASE_IDX 1
#define regVCN_UMSCH_IH_CTRL 0x0761
#define regVCN_UMSCH_IH_CTRL_BASE_IDX 1
#define regVCN_UMSCH_SYS_INT_EN 0x0762
#define regVCN_UMSCH_SYS_INT_EN_BASE_IDX 1
#define regVCN_UMSCH_SYS_INT_STATUS 0x0763
#define regVCN_UMSCH_SYS_INT_STATUS_BASE_IDX 1
#define regVCN_UMSCH_SYS_INT_ACK 0x0764
#define regVCN_UMSCH_SYS_INT_ACK_BASE_IDX 1
#define regVCN_UMSCH_SYS_INT_SRC 0x0765
#define regVCN_UMSCH_SYS_INT_SRC_BASE_IDX 1
#define regVCN_UMSCH_IH_CTX_CTRL 0x0766
#define regVCN_UMSCH_IH_CTX_CTRL_BASE_IDX 1
#define regVCN_UMSCH_CGC_CTRL 0x0767
#define regVCN_UMSCH_CGC_CTRL_BASE_IDX 1
#define regVCN_UMSCH_CGC_STATUS 0x0768
#define regVCN_UMSCH_CGC_STATUS_BASE_IDX 1
#define regVCN_UMSCH_CGC_MEM_CTRL 0x0769
#define regVCN_UMSCH_CGC_MEM_CTRL_BASE_IDX 1
#define regUVD_INTERNAL_REG_VIOLATION_8 0x076a
#define regUVD_INTERNAL_REG_VIOLATION_8_BASE_IDX 1
#define regUVD_UMSCH_FORCE 0x076b
#define regUVD_UMSCH_FORCE_BASE_IDX 1
#define regUVD_UMSCH_DEBUG_INDEX 0x076c
#define regUVD_UMSCH_DEBUG_INDEX_BASE_IDX 1
#define regUVD_UMSCH_DEBUG_DATA_LO 0x076d
#define regUVD_UMSCH_DEBUG_DATA_LO_BASE_IDX 1
#define regUVD_UMSCH_DEBUG_DATA_HI 0x076e
#define regUVD_UMSCH_DEBUG_DATA_HI_BASE_IDX 1
#define regUVD_UMSCH_DEBUG_UTCL2_TCIU_IF 0x076f
#define regUVD_UMSCH_DEBUG_UTCL2_TCIU_IF_BASE_IDX 1
#define regUMSCH_MES_RESET_CTRL 0x0770
#define regUMSCH_MES_RESET_CTRL_BASE_IDX 1
#define regVCN_MES_PRGRM_CNTR_START 0x0780
#define regVCN_MES_PRGRM_CNTR_START_BASE_IDX 1
#define regVCN_MES_INTR_ROUTINE_START 0x0781
#define regVCN_MES_INTR_ROUTINE_START_BASE_IDX 1
#define regVCN_MES_MTVEC_LO 0x0781
#define regVCN_MES_MTVEC_LO_BASE_IDX 1
#define regVCN_MES_INTR_ROUTINE_START_HI 0x0782
#define regVCN_MES_INTR_ROUTINE_START_HI_BASE_IDX 1
#define regVCN_MES_MTVEC_HI 0x0782
#define regVCN_MES_MTVEC_HI_BASE_IDX 1
#define regVCN_MES_CNTL 0x0787
#define regVCN_MES_CNTL_BASE_IDX 1
#define regVCN_MES_PIPE_PRIORITY_CNTS 0x0788
#define regVCN_MES_PIPE_PRIORITY_CNTS_BASE_IDX 1
#define regVCN_MES_PIPE0_PRIORITY 0x0789
#define regVCN_MES_PIPE0_PRIORITY_BASE_IDX 1
#define regVCN_MES_PIPE1_PRIORITY 0x078a
#define regVCN_MES_PIPE1_PRIORITY_BASE_IDX 1
#define regVCN_MES_PIPE2_PRIORITY 0x078b
#define regVCN_MES_PIPE2_PRIORITY_BASE_IDX 1
#define regVCN_MES_PIPE3_PRIORITY 0x078c
#define regVCN_MES_PIPE3_PRIORITY_BASE_IDX 1
#define regVCN_MES_HEADER_DUMP 0x078d
#define regVCN_MES_HEADER_DUMP_BASE_IDX 1
#define regVCN_MES_MIE_LO 0x078e
#define regVCN_MES_MIE_LO_BASE_IDX 1
#define regVCN_MES_MIE_HI 0x078f
#define regVCN_MES_MIE_HI_BASE_IDX 1
#define regVCN_MES_INTERRUPT 0x0790
#define regVCN_MES_INTERRUPT_BASE_IDX 1
#define regVCN_MES_SCRATCH_INDEX 0x0791
#define regVCN_MES_SCRATCH_INDEX_BASE_IDX 1
#define regVCN_MES_SCRATCH_DATA 0x0792
#define regVCN_MES_SCRATCH_DATA_BASE_IDX 1
#define regVCN_MES_INSTR_PNTR 0x0793
#define regVCN_MES_INSTR_PNTR_BASE_IDX 1
#define regVCN_MES_MSCRATCH_HI 0x0794
#define regVCN_MES_MSCRATCH_HI_BASE_IDX 1
#define regVCN_MES_MSCRATCH_LO 0x0795
#define regVCN_MES_MSCRATCH_LO_BASE_IDX 1
#define regVCN_MES_MSTATUS_LO 0x0796
#define regVCN_MES_MSTATUS_LO_BASE_IDX 1
#define regVCN_MES_MSTATUS_HI 0x0797
#define regVCN_MES_MSTATUS_HI_BASE_IDX 1
#define regVCN_MES_MEPC_LO 0x0798
#define regVCN_MES_MEPC_LO_BASE_IDX 1
#define regVCN_MES_MEPC_HI 0x0799
#define regVCN_MES_MEPC_HI_BASE_IDX 1
#define regVCN_MES_MCAUSE_LO 0x079a
#define regVCN_MES_MCAUSE_LO_BASE_IDX 1
#define regVCN_MES_MCAUSE_HI 0x079b
#define regVCN_MES_MCAUSE_HI_BASE_IDX 1
#define regVCN_MES_MBADADDR_LO 0x079c
#define regVCN_MES_MBADADDR_LO_BASE_IDX 1
#define regVCN_MES_MBADADDR_HI 0x079d
#define regVCN_MES_MBADADDR_HI_BASE_IDX 1
#define regVCN_MES_MIP_LO 0x079e
#define regVCN_MES_MIP_LO_BASE_IDX 1
#define regVCN_MES_MIP_HI 0x079f
#define regVCN_MES_MIP_HI_BASE_IDX 1
#define regVCN_MES_IC_OP_CNTL 0x07a0
#define regVCN_MES_IC_OP_CNTL_BASE_IDX 1
#define regVCN_MES_MCYCLE_LO 0x07a6
#define regVCN_MES_MCYCLE_LO_BASE_IDX 1
#define regVCN_MES_MCYCLE_HI 0x07a7
#define regVCN_MES_MCYCLE_HI_BASE_IDX 1
#define regVCN_MES_MTIME_LO 0x07a8
#define regVCN_MES_MTIME_LO_BASE_IDX 1
#define regVCN_MES_MTIME_HI 0x07a9
#define regVCN_MES_MTIME_HI_BASE_IDX 1
#define regVCN_MES_MINSTRET_LO 0x07aa
#define regVCN_MES_MINSTRET_LO_BASE_IDX 1
#define regVCN_MES_MINSTRET_HI 0x07ab
#define regVCN_MES_MINSTRET_HI_BASE_IDX 1
#define regVCN_MES_MISA_LO 0x07ac
#define regVCN_MES_MISA_LO_BASE_IDX 1
#define regVCN_MES_MISA_HI 0x07ad
#define regVCN_MES_MISA_HI_BASE_IDX 1
#define regVCN_MES_MVENDORID_LO 0x07ae
#define regVCN_MES_MVENDORID_LO_BASE_IDX 1
#define regVCN_MES_MVENDORID_HI 0x07af
#define regVCN_MES_MVENDORID_HI_BASE_IDX 1
#define regVCN_MES_MARCHID_LO 0x07b0
#define regVCN_MES_MARCHID_LO_BASE_IDX 1
#define regVCN_MES_MARCHID_HI 0x07b1
#define regVCN_MES_MARCHID_HI_BASE_IDX 1
#define regVCN_MES_MIMPID_LO 0x07b2
#define regVCN_MES_MIMPID_LO_BASE_IDX 1
#define regVCN_MES_MIMPID_HI 0x07b3
#define regVCN_MES_MIMPID_HI_BASE_IDX 1
#define regVCN_MES_MHARTID_LO 0x07b4
#define regVCN_MES_MHARTID_LO_BASE_IDX 1
#define regVCN_MES_MHARTID_HI 0x07b5
#define regVCN_MES_MHARTID_HI_BASE_IDX 1
#define regVCN_MES_DC_BASE_CNTL 0x07b6
#define regVCN_MES_DC_BASE_CNTL_BASE_IDX 1
#define regVCN_MES_DC_OP_CNTL 0x07b7
#define regVCN_MES_DC_OP_CNTL_BASE_IDX 1
#define regVCN_MES_MTIMECMP_LO 0x07b8
#define regVCN_MES_MTIMECMP_LO_BASE_IDX 1
#define regVCN_MES_MTIMECMP_HI 0x07b9
#define regVCN_MES_MTIMECMP_HI_BASE_IDX 1
#define regVCN_MES_DEBUG_INTERRUPT_INSTR_PNTR 0x07c2
#define regVCN_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX 1
#define regVCN_MES_GP0_LO 0x07c3
#define regVCN_MES_GP0_LO_BASE_IDX 1
#define regVCN_MES_GP0_HI 0x07c4
#define regVCN_MES_GP0_HI_BASE_IDX 1
#define regVCN_MES_GP1_LO 0x07c5
#define regVCN_MES_GP1_LO_BASE_IDX 1
#define regVCN_MES_GP1_HI 0x07c6
#define regVCN_MES_GP1_HI_BASE_IDX 1
#define regVCN_MES_GP2_LO 0x07c7
#define regVCN_MES_GP2_LO_BASE_IDX 1
#define regVCN_MES_GP2_HI 0x07c8
#define regVCN_MES_GP2_HI_BASE_IDX 1
#define regVCN_MES_GP3_LO 0x07c9
#define regVCN_MES_GP3_LO_BASE_IDX 1
#define regVCN_MES_GP3_HI 0x07ca
#define regVCN_MES_GP3_HI_BASE_IDX 1
#define regVCN_MES_GP4_LO 0x07cb
#define regVCN_MES_GP4_LO_BASE_IDX 1
#define regVCN_MES_GP4_HI 0x07cc
#define regVCN_MES_GP4_HI_BASE_IDX 1
#define regVCN_MES_GP5_LO 0x07cd
#define regVCN_MES_GP5_LO_BASE_IDX 1
#define regVCN_MES_GP5_HI 0x07ce
#define regVCN_MES_GP5_HI_BASE_IDX 1
#define regVCN_MES_GP6_LO 0x07cf
#define regVCN_MES_GP6_LO_BASE_IDX 1
#define regVCN_MES_GP6_HI 0x07d0
#define regVCN_MES_GP6_HI_BASE_IDX 1
#define regVCN_MES_GP7_LO 0x07d1
#define regVCN_MES_GP7_LO_BASE_IDX 1
#define regVCN_MES_GP7_HI 0x07d2
#define regVCN_MES_GP7_HI_BASE_IDX 1
#define regVCN_MES_GP8_LO 0x07d3
#define regVCN_MES_GP8_LO_BASE_IDX 1
#define regVCN_MES_GP8_HI 0x07d4
#define regVCN_MES_GP8_HI_BASE_IDX 1
#define regVCN_MES_GP9_LO 0x07d5
#define regVCN_MES_GP9_LO_BASE_IDX 1
#define regVCN_MES_GP9_HI 0x07d6
#define regVCN_MES_GP9_HI_BASE_IDX 1
#define regVCN_MES_DM_INDEX_ADDR 0x0800
#define regVCN_MES_DM_INDEX_ADDR_BASE_IDX 1
#define regVCN_MES_DM_INDEX_DATA 0x0801
#define regVCN_MES_DM_INDEX_DATA_BASE_IDX 1
#define regVCN_MES_DBG_FROM_RST 0x0802
#define regVCN_MES_DBG_FROM_RST_BASE_IDX 1
#define regVCN_MES_LOCAL_BASE0_LO 0x0803
#define regVCN_MES_LOCAL_BASE0_LO_BASE_IDX 1
#define regVCN_MES_LOCAL_BASE0_HI 0x0804
#define regVCN_MES_LOCAL_BASE0_HI_BASE_IDX 1
#define regVCN_MES_LOCAL_MASK0_LO 0x0805
#define regVCN_MES_LOCAL_MASK0_LO_BASE_IDX 1
#define regVCN_MES_LOCAL_MASK0_HI 0x0806
#define regVCN_MES_LOCAL_MASK0_HI_BASE_IDX 1
#define regVCN_MES_LOCAL_APERTURE 0x0807
#define regVCN_MES_LOCAL_APERTURE_BASE_IDX 1
#define regVCN_MES_LOCAL_INSTR_BASE_LO 0x0808
#define regVCN_MES_LOCAL_INSTR_BASE_LO_BASE_IDX 1
#define regVCN_MES_LOCAL_INSTR_BASE_HI 0x0809
#define regVCN_MES_LOCAL_INSTR_BASE_HI_BASE_IDX 1
#define regVCN_MES_LOCAL_INSTR_MASK_LO 0x080a
#define regVCN_MES_LOCAL_INSTR_MASK_LO_BASE_IDX 1
#define regVCN_MES_LOCAL_INSTR_MASK_HI 0x080b
#define regVCN_MES_LOCAL_INSTR_MASK_HI_BASE_IDX 1
#define regVCN_MES_LOCAL_INSTR_APERTURE 0x080c
#define regVCN_MES_LOCAL_INSTR_APERTURE_BASE_IDX 1
#define regVCN_MES_LOCAL_SCRATCH_APERTURE 0x080d
#define regVCN_MES_LOCAL_SCRATCH_APERTURE_BASE_IDX 1
#define regVCN_MES_LOCAL_SCRATCH_BASE_LO 0x080e
#define regVCN_MES_LOCAL_SCRATCH_BASE_LO_BASE_IDX 1
#define regVCN_MES_LOCAL_SCRATCH_BASE_HI 0x080f
#define regVCN_MES_LOCAL_SCRATCH_BASE_HI_BASE_IDX 1
#define regVCN_MES_PERFCOUNT_CNTL 0x0819
#define regVCN_MES_PERFCOUNT_CNTL_BASE_IDX 1
#define regVCN_MES_PENDING_INTERRUPT 0x081a
#define regVCN_MES_PENDING_INTERRUPT_BASE_IDX 1
#define regVCN_MES_PRIV_LEVEL 0x081b
#define regVCN_MES_PRIV_LEVEL_BASE_IDX 1
#define regVCN_MES_PRIV_LEVEL_VIOLATION_STATUS 0x081c
#define regVCN_MES_PRIV_LEVEL_VIOLATION_STATUS_BASE_IDX 1
#define regVCN_MES_PRGRM_CNTR_START_HI 0x081d
#define regVCN_MES_PRGRM_CNTR_START_HI_BASE_IDX 1
#define regVCN_MES_DEBUG_INTERRUPT_INSTR_PNTR_HI 0x081e
#define regVCN_MES_DEBUG_INTERRUPT_INSTR_PNTR_HI_BASE_IDX 1
#define regVCN_MES_INTERRUPT_DATA_16 0x081f
#define regVCN_MES_INTERRUPT_DATA_16_BASE_IDX 1
#define regVCN_MES_INTERRUPT_DATA_17 0x0820
#define regVCN_MES_INTERRUPT_DATA_17_BASE_IDX 1
#define regVCN_MES_INTERRUPT_DATA_18 0x0821
#define regVCN_MES_INTERRUPT_DATA_18_BASE_IDX 1
#define regVCN_MES_INTERRUPT_DATA_19 0x0822
#define regVCN_MES_INTERRUPT_DATA_19_BASE_IDX 1
#define regVCN_MES_INTERRUPT_DATA_20 0x0823
#define regVCN_MES_INTERRUPT_DATA_20_BASE_IDX 1
#define regVCN_MES_INTERRUPT_DATA_21 0x0824
#define regVCN_MES_INTERRUPT_DATA_21_BASE_IDX 1
#define regVCN_MES_INTERRUPT_DATA_22 0x0825
#define regVCN_MES_INTERRUPT_DATA_22_BASE_IDX 1
#define regVCN_MES_INTERRUPT_DATA_23 0x0826
#define regVCN_MES_INTERRUPT_DATA_23_BASE_IDX 1
#define regVCN_MES_INTERRUPT_DATA_24 0x0827
#define regVCN_MES_INTERRUPT_DATA_24_BASE_IDX 1
#define regVCN_MES_INTERRUPT_DATA_25 0x0828
#define regVCN_MES_INTERRUPT_DATA_25_BASE_IDX 1
#define regVCN_MES_INTERRUPT_DATA_26 0x0829
#define regVCN_MES_INTERRUPT_DATA_26_BASE_IDX 1
#define regVCN_MES_INTERRUPT_DATA_27 0x082a
#define regVCN_MES_INTERRUPT_DATA_27_BASE_IDX 1
#define regVCN_MES_INTERRUPT_DATA_28 0x082b
#define regVCN_MES_INTERRUPT_DATA_28_BASE_IDX 1
#define regVCN_MES_INTERRUPT_DATA_29 0x082c
#define regVCN_MES_INTERRUPT_DATA_29_BASE_IDX 1
#define regVCN_MES_INTERRUPT_DATA_30 0x082d
#define regVCN_MES_INTERRUPT_DATA_30_BASE_IDX 1
#define regVCN_MES_INTERRUPT_DATA_31 0x082e
#define regVCN_MES_INTERRUPT_DATA_31_BASE_IDX 1
#define regVCN_MES_DC_APERTURE0_BASE 0x082f
#define regVCN_MES_DC_APERTURE0_BASE_BASE_IDX 1
#define regVCN_MES_DC_APERTURE0_MASK 0x0830
#define regVCN_MES_DC_APERTURE0_MASK_BASE_IDX 1
#define regVCN_MES_DC_APERTURE0_CNTL 0x0831
#define regVCN_MES_DC_APERTURE0_CNTL_BASE_IDX 1
#define regVCN_MES_DC_APERTURE1_BASE 0x0832
#define regVCN_MES_DC_APERTURE1_BASE_BASE_IDX 1
#define regVCN_MES_DC_APERTURE1_MASK 0x0833
#define regVCN_MES_DC_APERTURE1_MASK_BASE_IDX 1
#define regVCN_MES_DC_APERTURE1_CNTL 0x0834
#define regVCN_MES_DC_APERTURE1_CNTL_BASE_IDX 1
#define regVCN_MES_DC_APERTURE2_BASE 0x0835
#define regVCN_MES_DC_APERTURE2_BASE_BASE_IDX 1
#define regVCN_MES_DC_APERTURE2_MASK 0x0836
#define regVCN_MES_DC_APERTURE2_MASK_BASE_IDX 1
#define regVCN_MES_DC_APERTURE2_CNTL 0x0837
#define regVCN_MES_DC_APERTURE2_CNTL_BASE_IDX 1
#define regVCN_MES_DC_APERTURE3_BASE 0x0838
#define regVCN_MES_DC_APERTURE3_BASE_BASE_IDX 1
#define regVCN_MES_DC_APERTURE3_MASK 0x0839
#define regVCN_MES_DC_APERTURE3_MASK_BASE_IDX 1
#define regVCN_MES_DC_APERTURE3_CNTL 0x083a
#define regVCN_MES_DC_APERTURE3_CNTL_BASE_IDX 1
#define regVCN_MES_DC_APERTURE4_BASE 0x083b
#define regVCN_MES_DC_APERTURE4_BASE_BASE_IDX 1
#define regVCN_MES_DC_APERTURE4_MASK 0x083c
#define regVCN_MES_DC_APERTURE4_MASK_BASE_IDX 1
#define regVCN_MES_DC_APERTURE4_CNTL 0x083d
#define regVCN_MES_DC_APERTURE4_CNTL_BASE_IDX 1
#define regVCN_MES_DC_APERTURE5_BASE 0x083e
#define regVCN_MES_DC_APERTURE5_BASE_BASE_IDX 1
#define regVCN_MES_DC_APERTURE5_MASK 0x083f
#define regVCN_MES_DC_APERTURE5_MASK_BASE_IDX 1
#define regVCN_MES_DC_APERTURE5_CNTL 0x0840
#define regVCN_MES_DC_APERTURE5_CNTL_BASE_IDX 1
#define regVCN_MES_DC_APERTURE6_BASE 0x0841
#define regVCN_MES_DC_APERTURE6_BASE_BASE_IDX 1
#define regVCN_MES_DC_APERTURE6_MASK 0x0842
#define regVCN_MES_DC_APERTURE6_MASK_BASE_IDX 1
#define regVCN_MES_DC_APERTURE6_CNTL 0x0843
#define regVCN_MES_DC_APERTURE6_CNTL_BASE_IDX 1
#define regVCN_MES_DC_APERTURE7_BASE 0x0844
#define regVCN_MES_DC_APERTURE7_BASE_BASE_IDX 1
#define regVCN_MES_DC_APERTURE7_MASK 0x0845
#define regVCN_MES_DC_APERTURE7_MASK_BASE_IDX 1
#define regVCN_MES_DC_APERTURE7_CNTL 0x0846
#define regVCN_MES_DC_APERTURE7_CNTL_BASE_IDX 1
#define regVCN_MES_DC_APERTURE8_BASE 0x0847
#define regVCN_MES_DC_APERTURE8_BASE_BASE_IDX 1
#define regVCN_MES_DC_APERTURE8_MASK 0x0848
#define regVCN_MES_DC_APERTURE8_MASK_BASE_IDX 1
#define regVCN_MES_DC_APERTURE8_CNTL 0x0849
#define regVCN_MES_DC_APERTURE8_CNTL_BASE_IDX 1
#define regVCN_MES_DC_APERTURE9_BASE 0x084a
#define regVCN_MES_DC_APERTURE9_BASE_BASE_IDX 1
#define regVCN_MES_DC_APERTURE9_MASK 0x084b
#define regVCN_MES_DC_APERTURE9_MASK_BASE_IDX 1
#define regVCN_MES_DC_APERTURE9_CNTL 0x084c
#define regVCN_MES_DC_APERTURE9_CNTL_BASE_IDX 1
#define regVCN_MES_DC_APERTURE10_BASE 0x084d
#define regVCN_MES_DC_APERTURE10_BASE_BASE_IDX 1
#define regVCN_MES_DC_APERTURE10_MASK 0x084e
#define regVCN_MES_DC_APERTURE10_MASK_BASE_IDX 1
#define regVCN_MES_DC_APERTURE10_CNTL 0x084f
#define regVCN_MES_DC_APERTURE10_CNTL_BASE_IDX 1
#define regVCN_MES_DC_APERTURE11_BASE 0x0850
#define regVCN_MES_DC_APERTURE11_BASE_BASE_IDX 1
#define regVCN_MES_DC_APERTURE11_MASK 0x0851
#define regVCN_MES_DC_APERTURE11_MASK_BASE_IDX 1
#define regVCN_MES_DC_APERTURE11_CNTL 0x0852
#define regVCN_MES_DC_APERTURE11_CNTL_BASE_IDX 1
#define regVCN_MES_DC_APERTURE12_BASE 0x0853
#define regVCN_MES_DC_APERTURE12_BASE_BASE_IDX 1
#define regVCN_MES_DC_APERTURE12_MASK 0x0854
#define regVCN_MES_DC_APERTURE12_MASK_BASE_IDX 1
#define regVCN_MES_DC_APERTURE12_CNTL 0x0855
#define regVCN_MES_DC_APERTURE12_CNTL_BASE_IDX 1
#define regVCN_MES_DC_APERTURE13_BASE 0x0856
#define regVCN_MES_DC_APERTURE13_BASE_BASE_IDX 1
#define regVCN_MES_DC_APERTURE13_MASK 0x0857
#define regVCN_MES_DC_APERTURE13_MASK_BASE_IDX 1
#define regVCN_MES_DC_APERTURE13_CNTL 0x0858
#define regVCN_MES_DC_APERTURE13_CNTL_BASE_IDX 1
#define regVCN_MES_DC_APERTURE14_BASE 0x0859
#define regVCN_MES_DC_APERTURE14_BASE_BASE_IDX 1
#define regVCN_MES_DC_APERTURE14_MASK 0x085a
#define regVCN_MES_DC_APERTURE14_MASK_BASE_IDX 1
#define regVCN_MES_DC_APERTURE14_CNTL 0x085b
#define regVCN_MES_DC_APERTURE14_CNTL_BASE_IDX 1
#define regVCN_MES_DC_APERTURE15_BASE 0x085c
#define regVCN_MES_DC_APERTURE15_BASE_BASE_IDX 1
#define regVCN_MES_DC_APERTURE15_MASK 0x085d
#define regVCN_MES_DC_APERTURE15_MASK_BASE_IDX 1
#define regVCN_MES_DC_APERTURE15_CNTL 0x085e
#define regVCN_MES_DC_APERTURE15_CNTL_BASE_IDX 1
#define regVCN_HYP_ME1_PIPE0_VMID_CNTL 0x0890
#define regVCN_HYP_ME1_PIPE0_VMID_CNTL_BASE_IDX 1
#define regVCN_HYP_ME1_PIPE1_VMID_CNTL 0x0891
#define regVCN_HYP_ME1_PIPE1_VMID_CNTL_BASE_IDX 1
#define regVCN_MES_IC_BASE_LO 0x08d0
#define regVCN_MES_IC_BASE_LO_BASE_IDX 1
#define regVCN_MES_MIBASE_LO 0x08d0
#define regVCN_MES_MIBASE_LO_BASE_IDX 1
#define regVCN_MES_IC_BASE_HI 0x08d1
#define regVCN_MES_IC_BASE_HI_BASE_IDX 1
#define regVCN_MES_MIBASE_HI 0x08d1
#define regVCN_MES_MIBASE_HI_BASE_IDX 1
#define regVCN_MES_IC_BASE_CNTL 0x08d2
#define regVCN_MES_IC_BASE_CNTL_BASE_IDX 1
#define regVCN_MES_DC_BASE_LO 0x08d4
#define regVCN_MES_DC_BASE_LO_BASE_IDX 1
#define regVCN_MES_MDBASE_LO 0x08d4
#define regVCN_MES_MDBASE_LO_BASE_IDX 1
#define regVCN_MES_DC_BASE_HI 0x08d5
#define regVCN_MES_DC_BASE_HI_BASE_IDX 1
#define regVCN_MES_MDBASE_HI 0x08d5
#define regVCN_MES_MDBASE_HI_BASE_IDX 1
#define regVCN_MES_MIBOUND_LO 0x08db
#define regVCN_MES_MIBOUND_LO_BASE_IDX 1
#define regVCN_MES_MIBOUND_HI 0x08dc
#define regVCN_MES_MIBOUND_HI_BASE_IDX 1
#define regVCN_MES_MDBOUND_LO 0x08dd
#define regVCN_MES_MDBOUND_LO_BASE_IDX 1
#define regVCN_MES_MDBOUND_HI 0x08de
#define regVCN_MES_MDBOUND_HI_BASE_IDX 1
// addressBlock: uvdctxind
// base address: 0x0

882
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h
View File

@@ -6769,6 +6769,73 @@
#define VCN_RB4_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL
#define VCN_RB4_DB_CTRL__EN_MASK 0x40000000L
#define VCN_RB4_DB_CTRL__HIT_MASK 0x80000000L
//VCN_UMSCH_RB_DB_CTRL
#define VCN_UMSCH_RB_DB_CTRL__OFFSET__SHIFT 0x2
#define VCN_UMSCH_RB_DB_CTRL__EN__SHIFT 0x1e
#define VCN_UMSCH_RB_DB_CTRL__HIT__SHIFT 0x1f
#define VCN_UMSCH_RB_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL
#define VCN_UMSCH_RB_DB_CTRL__EN_MASK 0x40000000L
#define VCN_UMSCH_RB_DB_CTRL__HIT_MASK 0x80000000L
//VCN_AGDB_CTRL0
#define VCN_AGDB_CTRL0__OFFSET__SHIFT 0x2
#define VCN_AGDB_CTRL0__EN__SHIFT 0x1e
#define VCN_AGDB_CTRL0__HIT__SHIFT 0x1f
#define VCN_AGDB_CTRL0__OFFSET_MASK 0x0FFFFFFCL
#define VCN_AGDB_CTRL0__EN_MASK 0x40000000L
#define VCN_AGDB_CTRL0__HIT_MASK 0x80000000L
//VCN_AGDB_CTRL1
#define VCN_AGDB_CTRL1__OFFSET__SHIFT 0x2
#define VCN_AGDB_CTRL1__EN__SHIFT 0x1e
#define VCN_AGDB_CTRL1__HIT__SHIFT 0x1f
#define VCN_AGDB_CTRL1__OFFSET_MASK 0x0FFFFFFCL
#define VCN_AGDB_CTRL1__EN_MASK 0x40000000L
#define VCN_AGDB_CTRL1__HIT_MASK 0x80000000L
//VCN_AGDB_CTRL2
#define VCN_AGDB_CTRL2__OFFSET__SHIFT 0x2
#define VCN_AGDB_CTRL2__EN__SHIFT 0x1e
#define VCN_AGDB_CTRL2__HIT__SHIFT 0x1f
#define VCN_AGDB_CTRL2__OFFSET_MASK 0x0FFFFFFCL
#define VCN_AGDB_CTRL2__EN_MASK 0x40000000L
#define VCN_AGDB_CTRL2__HIT_MASK 0x80000000L
//VCN_AGDB_CTRL3
#define VCN_AGDB_CTRL3__OFFSET__SHIFT 0x2
#define VCN_AGDB_CTRL3__EN__SHIFT 0x1e
#define VCN_AGDB_CTRL3__HIT__SHIFT 0x1f
#define VCN_AGDB_CTRL3__OFFSET_MASK 0x0FFFFFFCL
#define VCN_AGDB_CTRL3__EN_MASK 0x40000000L
#define VCN_AGDB_CTRL3__HIT_MASK 0x80000000L
//VCN_AGDB_CTRL4
#define VCN_AGDB_CTRL4__OFFSET__SHIFT 0x2
#define VCN_AGDB_CTRL4__EN__SHIFT 0x1e
#define VCN_AGDB_CTRL4__HIT__SHIFT 0x1f
#define VCN_AGDB_CTRL4__OFFSET_MASK 0x0FFFFFFCL
#define VCN_AGDB_CTRL4__EN_MASK 0x40000000L
#define VCN_AGDB_CTRL4__HIT_MASK 0x80000000L
//VCN_AGDB_CTRL5
#define VCN_AGDB_CTRL5__OFFSET__SHIFT 0x2
#define VCN_AGDB_CTRL5__EN__SHIFT 0x1e
#define VCN_AGDB_CTRL5__HIT__SHIFT 0x1f
#define VCN_AGDB_CTRL5__OFFSET_MASK 0x0FFFFFFCL
#define VCN_AGDB_CTRL5__EN_MASK 0x40000000L
#define VCN_AGDB_CTRL5__HIT_MASK 0x80000000L
//VCN_AGDB_MASK0
#define VCN_AGDB_MASK0__MASK__SHIFT 0x2
#define VCN_AGDB_MASK0__MASK_MASK 0x0FFFFFFCL
//VCN_AGDB_MASK1
#define VCN_AGDB_MASK1__MASK__SHIFT 0x2
#define VCN_AGDB_MASK1__MASK_MASK 0x0FFFFFFCL
//VCN_AGDB_MASK2
#define VCN_AGDB_MASK2__MASK__SHIFT 0x2
#define VCN_AGDB_MASK2__MASK_MASK 0x0FFFFFFCL
//VCN_AGDB_MASK3
#define VCN_AGDB_MASK3__MASK__SHIFT 0x2
#define VCN_AGDB_MASK3__MASK_MASK 0x0FFFFFFCL
//VCN_AGDB_MASK4
#define VCN_AGDB_MASK4__MASK__SHIFT 0x2
#define VCN_AGDB_MASK4__MASK_MASK 0x0FFFFFFCL
//VCN_AGDB_MASK5
#define VCN_AGDB_MASK5__MASK__SHIFT 0x2
#define VCN_AGDB_MASK5__MASK_MASK 0x0FFFFFFCL
//VCN_RB_ENABLE
#define VCN_RB_ENABLE__RB_EN__SHIFT 0x0
#define VCN_RB_ENABLE__JPEG_RB_EN__SHIFT 0x1
@@ -8051,5 +8118,820 @@
#define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_LO_ACK_MASK 0x04000000L
#define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_HI_ACK_MASK 0x08000000L
//VCN_UMSCH_MES_UTCL1_CNTL
#define VCN_UMSCH_MES_UTCL1_CNTL__REDO_LATENCY__SHIFT 0x0
#define VCN_UMSCH_MES_UTCL1_CNTL__ForceSnoop__SHIFT 0x14
#define VCN_UMSCH_MES_UTCL1_CNTL__FragLimitMode__SHIFT 0x15
#define VCN_UMSCH_MES_UTCL1_CNTL__DropMode__SHIFT 0x16
#define VCN_UMSCH_MES_UTCL1_CNTL__Invalidate__SHIFT 0x17
#define VCN_UMSCH_MES_UTCL1_CNTL__REDO_LATENCY_MASK 0x000FFFFFL
#define VCN_UMSCH_MES_UTCL1_CNTL__ForceSnoop_MASK 0x00100000L
#define VCN_UMSCH_MES_UTCL1_CNTL__FragLimitMode_MASK 0x00200000L
#define VCN_UMSCH_MES_UTCL1_CNTL__DropMode_MASK 0x00400000L
#define VCN_UMSCH_MES_UTCL1_CNTL__Invalidate_MASK 0x00800000L
//VCN_UMSCH_MES_BUSY
#define VCN_UMSCH_MES_BUSY__MesScratchRamBusy__SHIFT 0x0
#define VCN_UMSCH_MES_BUSY__MesInstrCacheBusy__SHIFT 0x1
#define VCN_UMSCH_MES_BUSY__MesDataCacheBusy__SHIFT 0x2
#define VCN_UMSCH_MES_BUSY__MesBusy__SHIFT 0x3
#define VCN_UMSCH_MES_BUSY__MesLoadBusy__SHIFT 0x4
#define VCN_UMSCH_MES_BUSY__MesMutexBusy__SHIFT 0x5
#define VCN_UMSCH_MES_BUSY__MesThreadBusy__SHIFT 0x6
#define VCN_UMSCH_MES_BUSY__MesMessageBusy__SHIFT 0x8
#define VCN_UMSCH_MES_BUSY__MesTcBusy__SHIFT 0xa
#define VCN_UMSCH_MES_BUSY__MesDmaPending__SHIFT 0xc
#define VCN_UMSCH_MES_BUSY__MesScratchRamBusy_MASK 0x00000001L
#define VCN_UMSCH_MES_BUSY__MesInstrCacheBusy_MASK 0x00000002L
#define VCN_UMSCH_MES_BUSY__MesDataCacheBusy_MASK 0x00000004L
#define VCN_UMSCH_MES_BUSY__MesBusy_MASK 0x00000008L
#define VCN_UMSCH_MES_BUSY__MesLoadBusy_MASK 0x00000010L
#define VCN_UMSCH_MES_BUSY__MesMutexBusy_MASK 0x00000020L
#define VCN_UMSCH_MES_BUSY__MesThreadBusy_MASK 0x000000C0L
#define VCN_UMSCH_MES_BUSY__MesMessageBusy_MASK 0x00000300L
#define VCN_UMSCH_MES_BUSY__MesTcBusy_MASK 0x00000C00L
#define VCN_UMSCH_MES_BUSY__MesDmaPending_MASK 0x00003000L
//VCN_UMSCH_RB_BASE_LO
#define VCN_UMSCH_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6
#define VCN_UMSCH_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L
//VCN_UMSCH_RB_BASE_HI
#define VCN_UMSCH_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0
#define VCN_UMSCH_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL
//VCN_UMSCH_RB_SIZE
#define VCN_UMSCH_RB_SIZE__WPTR__SHIFT 0x4
#define VCN_UMSCH_RB_SIZE__WPTR_MASK 0x007FFFF0L
//VCN_UMSCH_RB_RPTR
#define VCN_UMSCH_RB_RPTR__WPTR__SHIFT 0x4
#define VCN_UMSCH_RB_RPTR__WPTR_MASK 0x007FFFF0L
//VCN_UMSCH_RB_WPTR
#define VCN_UMSCH_RB_WPTR__WPTR__SHIFT 0x4
#define VCN_UMSCH_RB_WPTR__WPTR_MASK 0x007FFFF0L
//VCN_UMSCH_MASTINT_EN
#define VCN_UMSCH_MASTINT_EN__OVERRUN_RST__SHIFT 0x0
#define VCN_UMSCH_MASTINT_EN__SYS_EN__SHIFT 0x2
#define VCN_UMSCH_MASTINT_EN__INT_OVERRUN__SHIFT 0x4
#define VCN_UMSCH_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L
#define VCN_UMSCH_MASTINT_EN__SYS_EN_MASK 0x00000004L
#define VCN_UMSCH_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L
//VCN_UMSCH_IH_CTRL
#define VCN_UMSCH_IH_CTRL__IH_SOFT_RESET__SHIFT 0x0
#define VCN_UMSCH_IH_CTRL__IH_STALL_EN__SHIFT 0x1
#define VCN_UMSCH_IH_CTRL__IH_STATUS_CLEAN__SHIFT 0x2
#define VCN_UMSCH_IH_CTRL__IH_VMID__SHIFT 0x3
#define VCN_UMSCH_IH_CTRL__IH_USER_DATA__SHIFT 0x7
#define VCN_UMSCH_IH_CTRL__IH_RINGID__SHIFT 0x13
#define VCN_UMSCH_IH_CTRL__IH_SOFT_RESET_MASK 0x00000001L
#define VCN_UMSCH_IH_CTRL__IH_STALL_EN_MASK 0x00000002L
#define VCN_UMSCH_IH_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L
#define VCN_UMSCH_IH_CTRL__IH_VMID_MASK 0x00000078L
#define VCN_UMSCH_IH_CTRL__IH_USER_DATA_MASK 0x0007FF80L
#define VCN_UMSCH_IH_CTRL__IH_RINGID_MASK 0x07F80000L
//VCN_UMSCH_SYS_INT_EN
#define VCN_UMSCH_SYS_INT_EN__INT0__SHIFT 0x0
#define VCN_UMSCH_SYS_INT_EN__INT1__SHIFT 0x1
#define VCN_UMSCH_SYS_INT_EN__INT2__SHIFT 0x2
#define VCN_UMSCH_SYS_INT_EN__INT3__SHIFT 0x3
#define VCN_UMSCH_SYS_INT_EN__INT4__SHIFT 0x4
#define VCN_UMSCH_SYS_INT_EN__INT5__SHIFT 0x5
#define VCN_UMSCH_SYS_INT_EN__INT6__SHIFT 0x6
#define VCN_UMSCH_SYS_INT_EN__INT7__SHIFT 0x7
#define VCN_UMSCH_SYS_INT_EN__INT0_MASK 0x00000001L
#define VCN_UMSCH_SYS_INT_EN__INT1_MASK 0x00000002L
#define VCN_UMSCH_SYS_INT_EN__INT2_MASK 0x00000004L
#define VCN_UMSCH_SYS_INT_EN__INT3_MASK 0x00000008L
#define VCN_UMSCH_SYS_INT_EN__INT4_MASK 0x00000010L
#define VCN_UMSCH_SYS_INT_EN__INT5_MASK 0x00000020L
#define VCN_UMSCH_SYS_INT_EN__INT6_MASK 0x00000040L
#define VCN_UMSCH_SYS_INT_EN__INT7_MASK 0x00000080L
//VCN_UMSCH_SYS_INT_STATUS
#define VCN_UMSCH_SYS_INT_STATUS__INT0__SHIFT 0x0
#define VCN_UMSCH_SYS_INT_STATUS__INT1__SHIFT 0x1
#define VCN_UMSCH_SYS_INT_STATUS__INT2__SHIFT 0x2
#define VCN_UMSCH_SYS_INT_STATUS__INT3__SHIFT 0x3
#define VCN_UMSCH_SYS_INT_STATUS__INT4__SHIFT 0x4
#define VCN_UMSCH_SYS_INT_STATUS__INT5__SHIFT 0x5
#define VCN_UMSCH_SYS_INT_STATUS__INT6__SHIFT 0x6
#define VCN_UMSCH_SYS_INT_STATUS__INT7__SHIFT 0x7
#define VCN_UMSCH_SYS_INT_STATUS__INT0_MASK 0x00000001L
#define VCN_UMSCH_SYS_INT_STATUS__INT1_MASK 0x00000002L
#define VCN_UMSCH_SYS_INT_STATUS__INT2_MASK 0x00000004L
#define VCN_UMSCH_SYS_INT_STATUS__INT3_MASK 0x00000008L
#define VCN_UMSCH_SYS_INT_STATUS__INT4_MASK 0x00000010L
#define VCN_UMSCH_SYS_INT_STATUS__INT5_MASK 0x00000020L
#define VCN_UMSCH_SYS_INT_STATUS__INT6_MASK 0x00000040L
#define VCN_UMSCH_SYS_INT_STATUS__INT7_MASK 0x00000080L
//VCN_UMSCH_SYS_INT_ACK
#define VCN_UMSCH_SYS_INT_ACK__INT0__SHIFT 0x0
#define VCN_UMSCH_SYS_INT_ACK__INT1__SHIFT 0x1
#define VCN_UMSCH_SYS_INT_ACK__INT2__SHIFT 0x2
#define VCN_UMSCH_SYS_INT_ACK__INT3__SHIFT 0x3
#define VCN_UMSCH_SYS_INT_ACK__INT4__SHIFT 0x4
#define VCN_UMSCH_SYS_INT_ACK__INT5__SHIFT 0x5
#define VCN_UMSCH_SYS_INT_ACK__INT6__SHIFT 0x6
#define VCN_UMSCH_SYS_INT_ACK__INT7__SHIFT 0x7
#define VCN_UMSCH_SYS_INT_ACK__INT0_MASK 0x00000001L
#define VCN_UMSCH_SYS_INT_ACK__INT1_MASK 0x00000002L
#define VCN_UMSCH_SYS_INT_ACK__INT2_MASK 0x00000004L
#define VCN_UMSCH_SYS_INT_ACK__INT3_MASK 0x00000008L
#define VCN_UMSCH_SYS_INT_ACK__INT4_MASK 0x00000010L
#define VCN_UMSCH_SYS_INT_ACK__INT5_MASK 0x00000020L
#define VCN_UMSCH_SYS_INT_ACK__INT6_MASK 0x00000040L
#define VCN_UMSCH_SYS_INT_ACK__INT7_MASK 0x00000080L
//VCN_UMSCH_SYS_INT_SRC
#define VCN_UMSCH_SYS_INT_SRC__INT0__SHIFT 0x0
#define VCN_UMSCH_SYS_INT_SRC__INT1__SHIFT 0x1
#define VCN_UMSCH_SYS_INT_SRC__INT2__SHIFT 0x2
#define VCN_UMSCH_SYS_INT_SRC__INT3__SHIFT 0x3
#define VCN_UMSCH_SYS_INT_SRC__INT4__SHIFT 0x4
#define VCN_UMSCH_SYS_INT_SRC__INT5__SHIFT 0x5
#define VCN_UMSCH_SYS_INT_SRC__INT6__SHIFT 0x6
#define VCN_UMSCH_SYS_INT_SRC__INT7__SHIFT 0x7
#define VCN_UMSCH_SYS_INT_SRC__INT0_MASK 0x00000001L
#define VCN_UMSCH_SYS_INT_SRC__INT1_MASK 0x00000002L
#define VCN_UMSCH_SYS_INT_SRC__INT2_MASK 0x00000004L
#define VCN_UMSCH_SYS_INT_SRC__INT3_MASK 0x00000008L
#define VCN_UMSCH_SYS_INT_SRC__INT4_MASK 0x00000010L
#define VCN_UMSCH_SYS_INT_SRC__INT5_MASK 0x00000020L
#define VCN_UMSCH_SYS_INT_SRC__INT6_MASK 0x00000040L
#define VCN_UMSCH_SYS_INT_SRC__INT7_MASK 0x00000080L
//VCN_UMSCH_IH_CTX_CTRL
#define VCN_UMSCH_IH_CTX_CTRL__IH_CTX_ID__SHIFT 0x0
#define VCN_UMSCH_IH_CTX_CTRL__IH_CTX_ID_MASK 0x0FFFFFFFL
//VCN_UMSCH_CGC_CTRL
#define VCN_UMSCH_CGC_CTRL__UMSCH_MODE__SHIFT 0x0
#define VCN_UMSCH_CGC_CTRL__UMSCH__SHIFT 0x1
#define VCN_UMSCH_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2
#define VCN_UMSCH_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6
#define VCN_UMSCH_CGC_CTRL__UMSCH_REG_CG_MODE__SHIFT 0xe
#define VCN_UMSCH_CGC_CTRL__UMSCH_MODE_MASK 0x00000001L
#define VCN_UMSCH_CGC_CTRL__UMSCH_MASK 0x00000002L
#define VCN_UMSCH_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL
#define VCN_UMSCH_CGC_CTRL__CLK_OFF_DELAY_MASK 0x00003FC0L
#define VCN_UMSCH_CGC_CTRL__UMSCH_REG_CG_MODE_MASK 0x00004000L
//VCN_UMSCH_CGC_STATUS
#define VCN_UMSCH_CGC_STATUS__UMSCH_CORE_ACTIVE__SHIFT 0x0
#define VCN_UMSCH_CGC_STATUS__UMSCH_CORE_ACTIVE_MASK 0x00000001L
//VCN_UMSCH_CGC_MEM_CTRL
#define VCN_UMSCH_CGC_MEM_CTRL__UMSCH_LS_EN_HW_ON__SHIFT 0x0
#define VCN_UMSCH_CGC_MEM_CTRL__UMSCH_LS_EN_SW_ON__SHIFT 0x1
#define VCN_UMSCH_CGC_MEM_CTRL__UMSCH_DS_EN__SHIFT 0x2
#define VCN_UMSCH_CGC_MEM_CTRL__UMSCH_SD_EN__SHIFT 0x3
#define VCN_UMSCH_CGC_MEM_CTRL__UMSCH_LS_EN_HW_ON_MASK 0x00000001L
#define VCN_UMSCH_CGC_MEM_CTRL__UMSCH_LS_EN_SW_ON_MASK 0x00000002L
#define VCN_UMSCH_CGC_MEM_CTRL__UMSCH_DS_EN_MASK 0x00000004L
#define VCN_UMSCH_CGC_MEM_CTRL__UMSCH_SD_EN_MASK 0x00000008L
//UVD_INTERNAL_REG_VIOLATION_8
#define UVD_INTERNAL_REG_VIOLATION_8__UVD_INTERNAL_REG_VIOLATION_8_ADDR__SHIFT 0x2
#define UVD_INTERNAL_REG_VIOLATION_8__UVD_INTERNAL_REG_VIOLATION_8_MASTER_ID__SHIFT 0x14
#define UVD_INTERNAL_REG_VIOLATION_8__UVD_INTERNAL_REG_VIOLATION_8_OP__SHIFT 0x18
#define UVD_INTERNAL_REG_VIOLATION_8__UVD_INTERNAL_REG_VIOLATION_8_ADDR_MASK 0x000FFFFCL
#define UVD_INTERNAL_REG_VIOLATION_8__UVD_INTERNAL_REG_VIOLATION_8_MASTER_ID_MASK 0x00F00000L
#define UVD_INTERNAL_REG_VIOLATION_8__UVD_INTERNAL_REG_VIOLATION_8_OP_MASK 0x01000000L
//UVD_UMSCH_FORCE
#define UVD_UMSCH_FORCE__IC_FORCE_GPUVM__SHIFT 0x0
#define UVD_UMSCH_FORCE__DC_FORCE_GPUVM__SHIFT 0x1
#define UVD_UMSCH_FORCE__FORCE_DROP_DISABLE__SHIFT 0x2
#define UVD_UMSCH_FORCE__IC_FORCE_GPUVM_MASK 0x00000001L
#define UVD_UMSCH_FORCE__DC_FORCE_GPUVM_MASK 0x00000002L
#define UVD_UMSCH_FORCE__FORCE_DROP_DISABLE_MASK 0x00000004L
//UVD_UMSCH_DEBUG_INDEX
#define UVD_UMSCH_DEBUG_INDEX__DEBUG_READ_ADDR__SHIFT 0x0
#define UVD_UMSCH_DEBUG_INDEX__DEBUG_ADDR_FREE_STR_DIS__SHIFT 0x1e
#define UVD_UMSCH_DEBUG_INDEX__DEBUG_RESET__SHIFT 0x1f
#define UVD_UMSCH_DEBUG_INDEX__DEBUG_READ_ADDR_MASK 0x0000001FL
#define UVD_UMSCH_DEBUG_INDEX__DEBUG_ADDR_FREE_STR_DIS_MASK 0x40000000L
#define UVD_UMSCH_DEBUG_INDEX__DEBUG_RESET_MASK 0x80000000L
//UVD_UMSCH_DEBUG_DATA_LO
#define UVD_UMSCH_DEBUG_DATA_LO__DEBUG_DATA_LO__SHIFT 0x0
#define UVD_UMSCH_DEBUG_DATA_LO__DEBUG_DATA_LO_MASK 0xFFFFFFFFL
//UVD_UMSCH_DEBUG_DATA_HI
#define UVD_UMSCH_DEBUG_DATA_HI__DEBUG_DATA_HI__SHIFT 0x0
#define UVD_UMSCH_DEBUG_DATA_HI__DEBUG_DATA_HI_MASK 0xFFFFFFFFL
//UVD_UMSCH_DEBUG_UTCL2_TCIU_IF
#define UVD_UMSCH_DEBUG_UTCL2_TCIU_IF__UTCL2_IC_NACK__SHIFT 0x0
#define UVD_UMSCH_DEBUG_UTCL2_TCIU_IF__UTCL2_DC_NACK__SHIFT 0x2
#define UVD_UMSCH_DEBUG_UTCL2_TCIU_IF__TCIU_IC_DROP__SHIFT 0x4
#define UVD_UMSCH_DEBUG_UTCL2_TCIU_IF__TCIU_DC_DROP__SHIFT 0x5
#define UVD_UMSCH_DEBUG_UTCL2_TCIU_IF__UTCL2_IC_NACK_MASK 0x00000003L
#define UVD_UMSCH_DEBUG_UTCL2_TCIU_IF__UTCL2_DC_NACK_MASK 0x0000000CL
#define UVD_UMSCH_DEBUG_UTCL2_TCIU_IF__TCIU_IC_DROP_MASK 0x00000010L
#define UVD_UMSCH_DEBUG_UTCL2_TCIU_IF__TCIU_DC_DROP_MASK 0x00000020L
//UMSCH_MES_RESET_CTRL
#define UMSCH_MES_RESET_CTRL__MES_CORE_SOFT_RESET__SHIFT 0x0
#define UMSCH_MES_RESET_CTRL__MES_CORE_SOFT_RESET_MASK 0x00000001L
//VCN_MES_PRGRM_CNTR_START
#define VCN_MES_PRGRM_CNTR_START__IP_START__SHIFT 0x0
#define VCN_MES_PRGRM_CNTR_START__IP_START_MASK 0xFFFFFFFFL
//VCN_MES_INTR_ROUTINE_START
#define VCN_MES_INTR_ROUTINE_START__IR_START__SHIFT 0x0
#define VCN_MES_INTR_ROUTINE_START__IR_START_MASK 0xFFFFFFFFL
//VCN_MES_MTVEC_LO
#define VCN_MES_MTVEC_LO__ADDR_LO__SHIFT 0x0
#define VCN_MES_MTVEC_LO__ADDR_LO_MASK 0xFFFFFFFFL
//VCN_MES_INTR_ROUTINE_START_HI
#define VCN_MES_INTR_ROUTINE_START_HI__IR_START__SHIFT 0x0
#define VCN_MES_INTR_ROUTINE_START_HI__IR_START_MASK 0xFFFFFFFFL
//VCN_MES_MTVEC_HI
#define VCN_MES_MTVEC_HI__ADDR_LO__SHIFT 0x0
#define VCN_MES_MTVEC_HI__ADDR_LO_MASK 0xFFFFFFFFL
//VCN_MES_CNTL
#define VCN_MES_CNTL__MES_INVALIDATE_ICACHE__SHIFT 0x4
#define VCN_MES_CNTL__MES_PIPE0_RESET__SHIFT 0x10
#define VCN_MES_CNTL__MES_PIPE1_RESET__SHIFT 0x11
#define VCN_MES_CNTL__MES_PIPE2_RESET__SHIFT 0x12
#define VCN_MES_CNTL__MES_PIPE3_RESET__SHIFT 0x13
#define VCN_MES_CNTL__MES_PIPE0_ACTIVE__SHIFT 0x1a
#define VCN_MES_CNTL__MES_PIPE1_ACTIVE__SHIFT 0x1b
#define VCN_MES_CNTL__MES_PIPE2_ACTIVE__SHIFT 0x1c
#define VCN_MES_CNTL__MES_PIPE3_ACTIVE__SHIFT 0x1d
#define VCN_MES_CNTL__MES_HALT__SHIFT 0x1e
#define VCN_MES_CNTL__MES_STEP__SHIFT 0x1f
#define VCN_MES_CNTL__MES_INVALIDATE_ICACHE_MASK 0x00000010L
#define VCN_MES_CNTL__MES_PIPE0_RESET_MASK 0x00010000L
#define VCN_MES_CNTL__MES_PIPE1_RESET_MASK 0x00020000L
#define VCN_MES_CNTL__MES_PIPE2_RESET_MASK 0x00040000L
#define VCN_MES_CNTL__MES_PIPE3_RESET_MASK 0x00080000L
#define VCN_MES_CNTL__MES_PIPE0_ACTIVE_MASK 0x04000000L
#define VCN_MES_CNTL__MES_PIPE1_ACTIVE_MASK 0x08000000L
#define VCN_MES_CNTL__MES_PIPE2_ACTIVE_MASK 0x10000000L
#define VCN_MES_CNTL__MES_PIPE3_ACTIVE_MASK 0x20000000L
#define VCN_MES_CNTL__MES_HALT_MASK 0x40000000L
#define VCN_MES_CNTL__MES_STEP_MASK 0x80000000L
//VCN_MES_PIPE_PRIORITY_CNTS
#define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
#define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
#define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
#define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
#define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL
#define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L
#define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L
#define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L
//VCN_MES_PIPE0_PRIORITY
#define VCN_MES_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
#define VCN_MES_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L
//VCN_MES_PIPE1_PRIORITY
#define VCN_MES_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
#define VCN_MES_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L
//VCN_MES_PIPE2_PRIORITY
#define VCN_MES_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
#define VCN_MES_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L
//VCN_MES_PIPE3_PRIORITY
#define VCN_MES_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
#define VCN_MES_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L
//VCN_MES_HEADER_DUMP
#define VCN_MES_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
#define VCN_MES_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL
//VCN_MES_MIE_LO
#define VCN_MES_MIE_LO__MES_INT__SHIFT 0x0
#define VCN_MES_MIE_LO__MES_INT_MASK 0xFFFFFFFFL
//VCN_MES_MIE_HI
#define VCN_MES_MIE_HI__MES_INT__SHIFT 0x0
#define VCN_MES_MIE_HI__MES_INT_MASK 0xFFFFFFFFL
//VCN_MES_INTERRUPT
#define VCN_MES_INTERRUPT__MES_INT__SHIFT 0x0
#define VCN_MES_INTERRUPT__MES_INT_MASK 0xFFFFFFFFL
//VCN_MES_SCRATCH_INDEX
#define VCN_MES_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
#define VCN_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f
#define VCN_MES_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL
#define VCN_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L
//VCN_MES_SCRATCH_DATA
#define VCN_MES_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
#define VCN_MES_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL
//VCN_MES_INSTR_PNTR
#define VCN_MES_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
#define VCN_MES_INSTR_PNTR__INSTR_PNTR_MASK 0x000FFFFFL
//VCN_MES_MSCRATCH_HI
#define VCN_MES_MSCRATCH_HI__DATA__SHIFT 0x0
#define VCN_MES_MSCRATCH_HI__DATA_MASK 0xFFFFFFFFL
//VCN_MES_MSCRATCH_LO
#define VCN_MES_MSCRATCH_LO__DATA__SHIFT 0x0
#define VCN_MES_MSCRATCH_LO__DATA_MASK 0xFFFFFFFFL
//VCN_MES_MSTATUS_LO
#define VCN_MES_MSTATUS_LO__STATUS_LO__SHIFT 0x0
#define VCN_MES_MSTATUS_LO__STATUS_LO_MASK 0xFFFFFFFFL
//VCN_MES_MSTATUS_HI
#define VCN_MES_MSTATUS_HI__STATUS_HI__SHIFT 0x0
#define VCN_MES_MSTATUS_HI__STATUS_HI_MASK 0xFFFFFFFFL
//VCN_MES_MEPC_LO
#define VCN_MES_MEPC_LO__MEPC_LO__SHIFT 0x0
#define VCN_MES_MEPC_LO__MEPC_LO_MASK 0xFFFFFFFFL
//VCN_MES_MEPC_HI
#define VCN_MES_MEPC_HI__MEPC_HI__SHIFT 0x0
#define VCN_MES_MEPC_HI__MEPC_HI_MASK 0xFFFFFFFFL
//VCN_MES_MCAUSE_LO
#define VCN_MES_MCAUSE_LO__CAUSE_LO__SHIFT 0x0
#define VCN_MES_MCAUSE_LO__CAUSE_LO_MASK 0xFFFFFFFFL
//VCN_MES_MCAUSE_HI
#define VCN_MES_MCAUSE_HI__CAUSE_HI__SHIFT 0x0
#define VCN_MES_MCAUSE_HI__CAUSE_HI_MASK 0xFFFFFFFFL
//VCN_MES_MBADADDR_LO
#define VCN_MES_MBADADDR_LO__ADDR_LO__SHIFT 0x0
#define VCN_MES_MBADADDR_LO__ADDR_LO_MASK 0xFFFFFFFFL
//VCN_MES_MBADADDR_HI
#define VCN_MES_MBADADDR_HI__ADDR_HI__SHIFT 0x0
#define VCN_MES_MBADADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL
//VCN_MES_MIP_LO
#define VCN_MES_MIP_LO__MIP_LO__SHIFT 0x0
#define VCN_MES_MIP_LO__MIP_LO_MASK 0xFFFFFFFFL
//VCN_MES_MIP_HI
#define VCN_MES_MIP_HI__MIP_HI__SHIFT 0x0
#define VCN_MES_MIP_HI__MIP_HI_MASK 0xFFFFFFFFL
//VCN_MES_IC_OP_CNTL
#define VCN_MES_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0
#define VCN_MES_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4
#define VCN_MES_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5
#define VCN_MES_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L
#define VCN_MES_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L
#define VCN_MES_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L
//VCN_MES_MCYCLE_LO
#define VCN_MES_MCYCLE_LO__CYCLE_LO__SHIFT 0x0
#define VCN_MES_MCYCLE_LO__CYCLE_LO_MASK 0xFFFFFFFFL
//VCN_MES_MCYCLE_HI
#define VCN_MES_MCYCLE_HI__CYCLE_HI__SHIFT 0x0
#define VCN_MES_MCYCLE_HI__CYCLE_HI_MASK 0xFFFFFFFFL
//VCN_MES_MTIME_LO
#define VCN_MES_MTIME_LO__TIME_LO__SHIFT 0x0
#define VCN_MES_MTIME_LO__TIME_LO_MASK 0xFFFFFFFFL
//VCN_MES_MTIME_HI
#define VCN_MES_MTIME_HI__TIME_HI__SHIFT 0x0
#define VCN_MES_MTIME_HI__TIME_HI_MASK 0xFFFFFFFFL
//VCN_MES_MINSTRET_LO
#define VCN_MES_MINSTRET_LO__INSTRET_LO__SHIFT 0x0
#define VCN_MES_MINSTRET_LO__INSTRET_LO_MASK 0xFFFFFFFFL
//VCN_MES_MINSTRET_HI
#define VCN_MES_MINSTRET_HI__INSTRET_HI__SHIFT 0x0
#define VCN_MES_MINSTRET_HI__INSTRET_HI_MASK 0xFFFFFFFFL
//VCN_MES_MISA_LO
#define VCN_MES_MISA_LO__MISA_LO__SHIFT 0x0
#define VCN_MES_MISA_LO__MISA_LO_MASK 0xFFFFFFFFL
//VCN_MES_MISA_HI
#define VCN_MES_MISA_HI__MISA_HI__SHIFT 0x0
#define VCN_MES_MISA_HI__MISA_HI_MASK 0xFFFFFFFFL
//VCN_MES_MVENDORID_LO
#define VCN_MES_MVENDORID_LO__MVENDORID_LO__SHIFT 0x0
#define VCN_MES_MVENDORID_LO__MVENDORID_LO_MASK 0xFFFFFFFFL
//VCN_MES_MVENDORID_HI
#define VCN_MES_MVENDORID_HI__MVENDORID_HI__SHIFT 0x0
#define VCN_MES_MVENDORID_HI__MVENDORID_HI_MASK 0xFFFFFFFFL
//VCN_MES_MARCHID_LO
#define VCN_MES_MARCHID_LO__MARCHID_LO__SHIFT 0x0
#define VCN_MES_MARCHID_LO__MARCHID_LO_MASK 0xFFFFFFFFL
//VCN_MES_MARCHID_HI
#define VCN_MES_MARCHID_HI__MARCHID_HI__SHIFT 0x0
#define VCN_MES_MARCHID_HI__MARCHID_HI_MASK 0xFFFFFFFFL
//VCN_MES_MIMPID_LO
#define VCN_MES_MIMPID_LO__MIMPID_LO__SHIFT 0x0
#define VCN_MES_MIMPID_LO__MIMPID_LO_MASK 0xFFFFFFFFL
//VCN_MES_MIMPID_HI
#define VCN_MES_MIMPID_HI__MIMPID_HI__SHIFT 0x0
#define VCN_MES_MIMPID_HI__MIMPID_HI_MASK 0xFFFFFFFFL
//VCN_MES_MHARTID_LO
#define VCN_MES_MHARTID_LO__MHARTID_LO__SHIFT 0x0
#define VCN_MES_MHARTID_LO__MHARTID_LO_MASK 0xFFFFFFFFL
//VCN_MES_MHARTID_HI
#define VCN_MES_MHARTID_HI__MHARTID_HI__SHIFT 0x0
#define VCN_MES_MHARTID_HI__MHARTID_HI_MASK 0xFFFFFFFFL
//VCN_MES_DC_BASE_CNTL
#define VCN_MES_DC_BASE_CNTL__VMID__SHIFT 0x0
#define VCN_MES_DC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18
#define VCN_MES_DC_BASE_CNTL__VMID_MASK 0x0000000FL
#define VCN_MES_DC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L
//VCN_MES_DC_OP_CNTL
#define VCN_MES_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT 0x0
#define VCN_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT 0x1
#define VCN_MES_DC_OP_CNTL__BYPASS_ALL__SHIFT 0x2
#define VCN_MES_DC_OP_CNTL__DEPRECATED__SHIFT 0x3
#define VCN_MES_DC_OP_CNTL__DEPRACATED__SHIFT 0x4
#define VCN_MES_DC_OP_CNTL__INVALIDATE_DCACHE_MASK 0x00000001L
#define VCN_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK 0x00000002L
#define VCN_MES_DC_OP_CNTL__BYPASS_ALL_MASK 0x00000004L
#define VCN_MES_DC_OP_CNTL__DEPRECATED_MASK 0x00000008L
#define VCN_MES_DC_OP_CNTL__DEPRACATED_MASK 0x00000010L
//VCN_MES_MTIMECMP_LO
#define VCN_MES_MTIMECMP_LO__TIME_LO__SHIFT 0x0
#define VCN_MES_MTIMECMP_LO__TIME_LO_MASK 0xFFFFFFFFL
//VCN_MES_MTIMECMP_HI
#define VCN_MES_MTIMECMP_HI__TIME_HI__SHIFT 0x0
#define VCN_MES_MTIMECMP_HI__TIME_HI_MASK 0xFFFFFFFFL
//VCN_MES_DEBUG_INTERRUPT_INSTR_PNTR
#define VCN_MES_DEBUG_INTERRUPT_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
#define VCN_MES_DEBUG_INTERRUPT_INSTR_PNTR__INSTR_PNTR_MASK 0xFFFFFFFFL
//VCN_MES_GP0_LO
#define VCN_MES_GP0_LO__PG_VIRT_HALTED__SHIFT 0x0
#define VCN_MES_GP0_LO__DATA__SHIFT 0x1
#define VCN_MES_GP0_LO__PG_VIRT_HALTED_MASK 0x00000001L
#define VCN_MES_GP0_LO__DATA_MASK 0xFFFFFFFEL
//VCN_MES_GP0_HI
#define VCN_MES_GP0_HI__M_RET_ADDR__SHIFT 0x0
#define VCN_MES_GP0_HI__M_RET_ADDR_MASK 0xFFFFFFFFL
//VCN_MES_GP1_LO
#define VCN_MES_GP1_LO__RD_WR_SELECT_LO__SHIFT 0x0
#define VCN_MES_GP1_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL
//VCN_MES_GP1_HI
#define VCN_MES_GP1_HI__RD_WR_SELECT_HI__SHIFT 0x0
#define VCN_MES_GP1_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL
//VCN_MES_GP2_LO
#define VCN_MES_GP2_LO__STACK_PNTR_LO__SHIFT 0x0
#define VCN_MES_GP2_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL
//VCN_MES_GP2_HI
#define VCN_MES_GP2_HI__STACK_PNTR_HI__SHIFT 0x0
#define VCN_MES_GP2_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL
//VCN_MES_GP3_LO
#define VCN_MES_GP3_LO__DATA__SHIFT 0x0
#define VCN_MES_GP3_LO__DATA_MASK 0xFFFFFFFFL
//VCN_MES_GP3_HI
#define VCN_MES_GP3_HI__DATA__SHIFT 0x0
#define VCN_MES_GP3_HI__DATA_MASK 0xFFFFFFFFL
//VCN_MES_GP4_LO
#define VCN_MES_GP4_LO__DATA__SHIFT 0x0
#define VCN_MES_GP4_LO__DATA_MASK 0xFFFFFFFFL
//VCN_MES_GP4_HI
#define VCN_MES_GP4_HI__DATA__SHIFT 0x0
#define VCN_MES_GP4_HI__DATA_MASK 0xFFFFFFFFL
//VCN_MES_GP5_LO
#define VCN_MES_GP5_LO__PG_VIRT_HALTED__SHIFT 0x0
#define VCN_MES_GP5_LO__DATA__SHIFT 0x1
#define VCN_MES_GP5_LO__PG_VIRT_HALTED_MASK 0x00000001L
#define VCN_MES_GP5_LO__DATA_MASK 0xFFFFFFFEL
//VCN_MES_GP5_HI
#define VCN_MES_GP5_HI__M_RET_ADDR__SHIFT 0x0
#define VCN_MES_GP5_HI__M_RET_ADDR_MASK 0xFFFFFFFFL
//VCN_MES_GP6_LO
#define VCN_MES_GP6_LO__RD_WR_SELECT_LO__SHIFT 0x0
#define VCN_MES_GP6_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL
//VCN_MES_GP6_HI
#define VCN_MES_GP6_HI__RD_WR_SELECT_HI__SHIFT 0x0
#define VCN_MES_GP6_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL
//VCN_MES_GP7_LO
#define VCN_MES_GP7_LO__STACK_PNTR_LO__SHIFT 0x0
#define VCN_MES_GP7_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL
//VCN_MES_GP7_HI
#define VCN_MES_GP7_HI__STACK_PNTR_HI__SHIFT 0x0
#define VCN_MES_GP7_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL
//VCN_MES_GP8_LO
#define VCN_MES_GP8_LO__DATA__SHIFT 0x0
#define VCN_MES_GP8_LO__DATA_MASK 0xFFFFFFFFL
//VCN_MES_GP8_HI
#define VCN_MES_GP8_HI__DATA__SHIFT 0x0
#define VCN_MES_GP8_HI__DATA_MASK 0xFFFFFFFFL
//VCN_MES_GP9_LO
#define VCN_MES_GP9_LO__DATA__SHIFT 0x0
#define VCN_MES_GP9_LO__DATA_MASK 0xFFFFFFFFL
//VCN_MES_GP9_HI
#define VCN_MES_GP9_HI__DATA__SHIFT 0x0
#define VCN_MES_GP9_HI__DATA_MASK 0xFFFFFFFFL
//VCN_MES_DM_INDEX_ADDR
#define VCN_MES_DM_INDEX_ADDR__ADDR__SHIFT 0x0
#define VCN_MES_DM_INDEX_ADDR__ADDR_MASK 0xFFFFFFFFL
//VCN_MES_DM_INDEX_DATA
#define VCN_MES_DM_INDEX_DATA__DATA__SHIFT 0x0
#define VCN_MES_DM_INDEX_DATA__DATA_MASK 0xFFFFFFFFL
//VCN_MES_DBG_FROM_RST
#define VCN_MES_DBG_FROM_RST__CONTROL__SHIFT 0x0
#define VCN_MES_DBG_FROM_RST__CONTROL_MASK 0x00000001L
//VCN_MES_LOCAL_BASE0_LO
#define VCN_MES_LOCAL_BASE0_LO__BASE0_LO__SHIFT 0x10
#define VCN_MES_LOCAL_BASE0_LO__BASE0_LO_MASK 0xFFFF0000L
//VCN_MES_LOCAL_BASE0_HI
#define VCN_MES_LOCAL_BASE0_HI__BASE0_HI__SHIFT 0x0
#define VCN_MES_LOCAL_BASE0_HI__BASE0_HI_MASK 0x0000FFFFL
//VCN_MES_LOCAL_MASK0_LO
#define VCN_MES_LOCAL_MASK0_LO__MASK0_LO__SHIFT 0x10
#define VCN_MES_LOCAL_MASK0_LO__MASK0_LO_MASK 0xFFFF0000L
//VCN_MES_LOCAL_MASK0_HI
#define VCN_MES_LOCAL_MASK0_HI__MASK0_HI__SHIFT 0x0
#define VCN_MES_LOCAL_MASK0_HI__MASK0_HI_MASK 0x0000FFFFL
//VCN_MES_LOCAL_APERTURE
#define VCN_MES_LOCAL_APERTURE__APERTURE__SHIFT 0x0
#define VCN_MES_LOCAL_APERTURE__APERTURE_MASK 0x00000007L
//VCN_MES_LOCAL_INSTR_BASE_LO
#define VCN_MES_LOCAL_INSTR_BASE_LO__BASE_LO__SHIFT 0x10
#define VCN_MES_LOCAL_INSTR_BASE_LO__BASE_LO_MASK 0xFFFF0000L
//VCN_MES_LOCAL_INSTR_BASE_HI
#define VCN_MES_LOCAL_INSTR_BASE_HI__BASE_HI__SHIFT 0x0
#define VCN_MES_LOCAL_INSTR_BASE_HI__BASE_HI_MASK 0x0000FFFFL
//VCN_MES_LOCAL_INSTR_MASK_LO
#define VCN_MES_LOCAL_INSTR_MASK_LO__MASK_LO__SHIFT 0x10
#define VCN_MES_LOCAL_INSTR_MASK_LO__MASK_LO_MASK 0xFFFF0000L
//VCN_MES_LOCAL_INSTR_MASK_HI
#define VCN_MES_LOCAL_INSTR_MASK_HI__MASK_HI__SHIFT 0x0
#define VCN_MES_LOCAL_INSTR_MASK_HI__MASK_HI_MASK 0x0000FFFFL
//VCN_MES_LOCAL_INSTR_APERTURE
#define VCN_MES_LOCAL_INSTR_APERTURE__APERTURE__SHIFT 0x0
#define VCN_MES_LOCAL_INSTR_APERTURE__APERTURE_MASK 0x00000007L
//VCN_MES_LOCAL_SCRATCH_APERTURE
#define VCN_MES_LOCAL_SCRATCH_APERTURE__APERTURE__SHIFT 0x0
#define VCN_MES_LOCAL_SCRATCH_APERTURE__APERTURE_MASK 0x00000007L
//VCN_MES_LOCAL_SCRATCH_BASE_LO
#define VCN_MES_LOCAL_SCRATCH_BASE_LO__BASE_LO__SHIFT 0x10
#define VCN_MES_LOCAL_SCRATCH_BASE_LO__BASE_LO_MASK 0xFFFF0000L
//VCN_MES_LOCAL_SCRATCH_BASE_HI
#define VCN_MES_LOCAL_SCRATCH_BASE_HI__BASE_HI__SHIFT 0x0
#define VCN_MES_LOCAL_SCRATCH_BASE_HI__BASE_HI_MASK 0x0000FFFFL
//VCN_MES_PERFCOUNT_CNTL
#define VCN_MES_PERFCOUNT_CNTL__EVENT_SEL__SHIFT 0x0
#define VCN_MES_PERFCOUNT_CNTL__EVENT_SEL_MASK 0x0000001FL
//VCN_MES_PENDING_INTERRUPT
#define VCN_MES_PENDING_INTERRUPT__PENDING_INTERRUPT__SHIFT 0x0
#define VCN_MES_PENDING_INTERRUPT__PENDING_INTERRUPT_MASK 0xFFFFFFFFL
//VCN_MES_PRIV_LEVEL
#define VCN_MES_PRIV_LEVEL__PRIV_LEVEL__SHIFT 0x0
#define VCN_MES_PRIV_LEVEL__GRBM_PRIV_LEVEL__SHIFT 0x1
#define VCN_MES_PRIV_LEVEL__PRIV_LEVEL_MASK 0x00000001L
#define VCN_MES_PRIV_LEVEL__GRBM_PRIV_LEVEL_MASK 0x00000002L
//VCN_MES_PRIV_LEVEL_VIOLATION_STATUS
#define VCN_MES_PRIV_LEVEL_VIOLATION_STATUS__PRIV_LEVEL_VIOLATION_OCCURRED__SHIFT 0x0
#define VCN_MES_PRIV_LEVEL_VIOLATION_STATUS__PRIV_LEVEL_VIOLATION_OP__SHIFT 0x1
#define VCN_MES_PRIV_LEVEL_VIOLATION_STATUS__PRIV_LEVEL_VIOLATION_ADDR__SHIFT 0x2
#define VCN_MES_PRIV_LEVEL_VIOLATION_STATUS__PRIV_LEVEL_VIOLATION_APERTURE__SHIFT 0x16
#define VCN_MES_PRIV_LEVEL_VIOLATION_STATUS__PRIV_LEVEL_VIOLATION_OCCURRED_MASK 0x00000001L
#define VCN_MES_PRIV_LEVEL_VIOLATION_STATUS__PRIV_LEVEL_VIOLATION_OP_MASK 0x00000002L
#define VCN_MES_PRIV_LEVEL_VIOLATION_STATUS__PRIV_LEVEL_VIOLATION_ADDR_MASK 0x003FFFFCL
#define VCN_MES_PRIV_LEVEL_VIOLATION_STATUS__PRIV_LEVEL_VIOLATION_APERTURE_MASK 0x01C00000L
//VCN_MES_PRGRM_CNTR_START_HI
#define VCN_MES_PRGRM_CNTR_START_HI__IP_START__SHIFT 0x0
#define VCN_MES_PRGRM_CNTR_START_HI__IP_START_MASK 0x3FFFFFFFL
//VCN_MES_DEBUG_INTERRUPT_INSTR_PNTR_HI
#define VCN_MES_DEBUG_INTERRUPT_INSTR_PNTR_HI__INSTR_PNTR__SHIFT 0x0
#define VCN_MES_DEBUG_INTERRUPT_INSTR_PNTR_HI__INSTR_PNTR_MASK 0x3FFFFFFFL
//VCN_MES_INTERRUPT_DATA_16
#define VCN_MES_INTERRUPT_DATA_16__DATA__SHIFT 0x0
#define VCN_MES_INTERRUPT_DATA_16__DATA_MASK 0xFFFFFFFFL
//VCN_MES_INTERRUPT_DATA_17
#define VCN_MES_INTERRUPT_DATA_17__DATA__SHIFT 0x0
#define VCN_MES_INTERRUPT_DATA_17__DATA_MASK 0xFFFFFFFFL
//VCN_MES_INTERRUPT_DATA_18
#define VCN_MES_INTERRUPT_DATA_18__DATA__SHIFT 0x0
#define VCN_MES_INTERRUPT_DATA_18__DATA_MASK 0xFFFFFFFFL
//VCN_MES_INTERRUPT_DATA_19
#define VCN_MES_INTERRUPT_DATA_19__DATA__SHIFT 0x0
#define VCN_MES_INTERRUPT_DATA_19__DATA_MASK 0xFFFFFFFFL
//VCN_MES_INTERRUPT_DATA_20
#define VCN_MES_INTERRUPT_DATA_20__DATA__SHIFT 0x0
#define VCN_MES_INTERRUPT_DATA_20__DATA_MASK 0xFFFFFFFFL
//VCN_MES_INTERRUPT_DATA_21
#define VCN_MES_INTERRUPT_DATA_21__DATA__SHIFT 0x0
#define VCN_MES_INTERRUPT_DATA_21__DATA_MASK 0xFFFFFFFFL
//VCN_MES_INTERRUPT_DATA_22
#define VCN_MES_INTERRUPT_DATA_22__DATA__SHIFT 0x0
#define VCN_MES_INTERRUPT_DATA_22__DATA_MASK 0xFFFFFFFFL
//VCN_MES_INTERRUPT_DATA_23
#define VCN_MES_INTERRUPT_DATA_23__DATA__SHIFT 0x0
#define VCN_MES_INTERRUPT_DATA_23__DATA_MASK 0xFFFFFFFFL
//VCN_MES_INTERRUPT_DATA_24
#define VCN_MES_INTERRUPT_DATA_24__DATA__SHIFT 0x0
#define VCN_MES_INTERRUPT_DATA_24__DATA_MASK 0xFFFFFFFFL
//VCN_MES_INTERRUPT_DATA_25
#define VCN_MES_INTERRUPT_DATA_25__DATA__SHIFT 0x0
#define VCN_MES_INTERRUPT_DATA_25__DATA_MASK 0xFFFFFFFFL
//VCN_MES_INTERRUPT_DATA_26
#define VCN_MES_INTERRUPT_DATA_26__DATA__SHIFT 0x0
#define VCN_MES_INTERRUPT_DATA_26__DATA_MASK 0xFFFFFFFFL
//VCN_MES_INTERRUPT_DATA_27
#define VCN_MES_INTERRUPT_DATA_27__DATA__SHIFT 0x0
#define VCN_MES_INTERRUPT_DATA_27__DATA_MASK 0xFFFFFFFFL
//VCN_MES_INTERRUPT_DATA_28
#define VCN_MES_INTERRUPT_DATA_28__DATA__SHIFT 0x0
#define VCN_MES_INTERRUPT_DATA_28__DATA_MASK 0xFFFFFFFFL
//VCN_MES_INTERRUPT_DATA_29
#define VCN_MES_INTERRUPT_DATA_29__DATA__SHIFT 0x0
#define VCN_MES_INTERRUPT_DATA_29__DATA_MASK 0xFFFFFFFFL
//VCN_MES_INTERRUPT_DATA_30
#define VCN_MES_INTERRUPT_DATA_30__DATA__SHIFT 0x0
#define VCN_MES_INTERRUPT_DATA_30__DATA_MASK 0xFFFFFFFFL
//VCN_MES_INTERRUPT_DATA_31
#define VCN_MES_INTERRUPT_DATA_31__DATA__SHIFT 0x0
#define VCN_MES_INTERRUPT_DATA_31__DATA_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE0_BASE
#define VCN_MES_DC_APERTURE0_BASE__BASE__SHIFT 0x0
#define VCN_MES_DC_APERTURE0_BASE__BASE_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE0_MASK
#define VCN_MES_DC_APERTURE0_MASK__MASK__SHIFT 0x0
#define VCN_MES_DC_APERTURE0_MASK__MASK_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE0_CNTL
#define VCN_MES_DC_APERTURE0_CNTL__VMID__SHIFT 0x0
#define VCN_MES_DC_APERTURE0_CNTL__BYPASS_MODE__SHIFT 0x4
#define VCN_MES_DC_APERTURE0_CNTL__VMID_MASK 0x0000000FL
#define VCN_MES_DC_APERTURE0_CNTL__BYPASS_MODE_MASK 0x00000010L
//VCN_MES_DC_APERTURE1_BASE
#define VCN_MES_DC_APERTURE1_BASE__BASE__SHIFT 0x0
#define VCN_MES_DC_APERTURE1_BASE__BASE_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE1_MASK
#define VCN_MES_DC_APERTURE1_MASK__MASK__SHIFT 0x0
#define VCN_MES_DC_APERTURE1_MASK__MASK_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE1_CNTL
#define VCN_MES_DC_APERTURE1_CNTL__VMID__SHIFT 0x0
#define VCN_MES_DC_APERTURE1_CNTL__BYPASS_MODE__SHIFT 0x4
#define VCN_MES_DC_APERTURE1_CNTL__VMID_MASK 0x0000000FL
#define VCN_MES_DC_APERTURE1_CNTL__BYPASS_MODE_MASK 0x00000010L
//VCN_MES_DC_APERTURE2_BASE
#define VCN_MES_DC_APERTURE2_BASE__BASE__SHIFT 0x0
#define VCN_MES_DC_APERTURE2_BASE__BASE_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE2_MASK
#define VCN_MES_DC_APERTURE2_MASK__MASK__SHIFT 0x0
#define VCN_MES_DC_APERTURE2_MASK__MASK_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE2_CNTL
#define VCN_MES_DC_APERTURE2_CNTL__VMID__SHIFT 0x0
#define VCN_MES_DC_APERTURE2_CNTL__BYPASS_MODE__SHIFT 0x4
#define VCN_MES_DC_APERTURE2_CNTL__VMID_MASK 0x0000000FL
#define VCN_MES_DC_APERTURE2_CNTL__BYPASS_MODE_MASK 0x00000010L
//VCN_MES_DC_APERTURE3_BASE
#define VCN_MES_DC_APERTURE3_BASE__BASE__SHIFT 0x0
#define VCN_MES_DC_APERTURE3_BASE__BASE_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE3_MASK
#define VCN_MES_DC_APERTURE3_MASK__MASK__SHIFT 0x0
#define VCN_MES_DC_APERTURE3_MASK__MASK_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE3_CNTL
#define VCN_MES_DC_APERTURE3_CNTL__VMID__SHIFT 0x0
#define VCN_MES_DC_APERTURE3_CNTL__BYPASS_MODE__SHIFT 0x4
#define VCN_MES_DC_APERTURE3_CNTL__VMID_MASK 0x0000000FL
#define VCN_MES_DC_APERTURE3_CNTL__BYPASS_MODE_MASK 0x00000010L
//VCN_MES_DC_APERTURE4_BASE
#define VCN_MES_DC_APERTURE4_BASE__BASE__SHIFT 0x0
#define VCN_MES_DC_APERTURE4_BASE__BASE_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE4_MASK
#define VCN_MES_DC_APERTURE4_MASK__MASK__SHIFT 0x0
#define VCN_MES_DC_APERTURE4_MASK__MASK_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE4_CNTL
#define VCN_MES_DC_APERTURE4_CNTL__VMID__SHIFT 0x0
#define VCN_MES_DC_APERTURE4_CNTL__BYPASS_MODE__SHIFT 0x4
#define VCN_MES_DC_APERTURE4_CNTL__VMID_MASK 0x0000000FL
#define VCN_MES_DC_APERTURE4_CNTL__BYPASS_MODE_MASK 0x00000010L
//VCN_MES_DC_APERTURE5_BASE
#define VCN_MES_DC_APERTURE5_BASE__BASE__SHIFT 0x0
#define VCN_MES_DC_APERTURE5_BASE__BASE_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE5_MASK
#define VCN_MES_DC_APERTURE5_MASK__MASK__SHIFT 0x0
#define VCN_MES_DC_APERTURE5_MASK__MASK_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE5_CNTL
#define VCN_MES_DC_APERTURE5_CNTL__VMID__SHIFT 0x0
#define VCN_MES_DC_APERTURE5_CNTL__BYPASS_MODE__SHIFT 0x4
#define VCN_MES_DC_APERTURE5_CNTL__VMID_MASK 0x0000000FL
#define VCN_MES_DC_APERTURE5_CNTL__BYPASS_MODE_MASK 0x00000010L
//VCN_MES_DC_APERTURE6_BASE
#define VCN_MES_DC_APERTURE6_BASE__BASE__SHIFT 0x0
#define VCN_MES_DC_APERTURE6_BASE__BASE_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE6_MASK
#define VCN_MES_DC_APERTURE6_MASK__MASK__SHIFT 0x0
#define VCN_MES_DC_APERTURE6_MASK__MASK_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE6_CNTL
#define VCN_MES_DC_APERTURE6_CNTL__VMID__SHIFT 0x0
#define VCN_MES_DC_APERTURE6_CNTL__BYPASS_MODE__SHIFT 0x4
#define VCN_MES_DC_APERTURE6_CNTL__VMID_MASK 0x0000000FL
#define VCN_MES_DC_APERTURE6_CNTL__BYPASS_MODE_MASK 0x00000010L
//VCN_MES_DC_APERTURE7_BASE
#define VCN_MES_DC_APERTURE7_BASE__BASE__SHIFT 0x0
#define VCN_MES_DC_APERTURE7_BASE__BASE_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE7_MASK
#define VCN_MES_DC_APERTURE7_MASK__MASK__SHIFT 0x0
#define VCN_MES_DC_APERTURE7_MASK__MASK_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE7_CNTL
#define VCN_MES_DC_APERTURE7_CNTL__VMID__SHIFT 0x0
#define VCN_MES_DC_APERTURE7_CNTL__BYPASS_MODE__SHIFT 0x4
#define VCN_MES_DC_APERTURE7_CNTL__VMID_MASK 0x0000000FL
#define VCN_MES_DC_APERTURE7_CNTL__BYPASS_MODE_MASK 0x00000010L
//VCN_MES_DC_APERTURE8_BASE
#define VCN_MES_DC_APERTURE8_BASE__BASE__SHIFT 0x0
#define VCN_MES_DC_APERTURE8_BASE__BASE_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE8_MASK
#define VCN_MES_DC_APERTURE8_MASK__MASK__SHIFT 0x0
#define VCN_MES_DC_APERTURE8_MASK__MASK_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE8_CNTL
#define VCN_MES_DC_APERTURE8_CNTL__VMID__SHIFT 0x0
#define VCN_MES_DC_APERTURE8_CNTL__BYPASS_MODE__SHIFT 0x4
#define VCN_MES_DC_APERTURE8_CNTL__VMID_MASK 0x0000000FL
#define VCN_MES_DC_APERTURE8_CNTL__BYPASS_MODE_MASK 0x00000010L
//VCN_MES_DC_APERTURE9_BASE
#define VCN_MES_DC_APERTURE9_BASE__BASE__SHIFT 0x0
#define VCN_MES_DC_APERTURE9_BASE__BASE_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE9_MASK
#define VCN_MES_DC_APERTURE9_MASK__MASK__SHIFT 0x0
#define VCN_MES_DC_APERTURE9_MASK__MASK_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE9_CNTL
#define VCN_MES_DC_APERTURE9_CNTL__VMID__SHIFT 0x0
#define VCN_MES_DC_APERTURE9_CNTL__BYPASS_MODE__SHIFT 0x4
#define VCN_MES_DC_APERTURE9_CNTL__VMID_MASK 0x0000000FL
#define VCN_MES_DC_APERTURE9_CNTL__BYPASS_MODE_MASK 0x00000010L
//VCN_MES_DC_APERTURE10_BASE
#define VCN_MES_DC_APERTURE10_BASE__BASE__SHIFT 0x0
#define VCN_MES_DC_APERTURE10_BASE__BASE_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE10_MASK
#define VCN_MES_DC_APERTURE10_MASK__MASK__SHIFT 0x0
#define VCN_MES_DC_APERTURE10_MASK__MASK_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE10_CNTL
#define VCN_MES_DC_APERTURE10_CNTL__VMID__SHIFT 0x0
#define VCN_MES_DC_APERTURE10_CNTL__BYPASS_MODE__SHIFT 0x4
#define VCN_MES_DC_APERTURE10_CNTL__VMID_MASK 0x0000000FL
#define VCN_MES_DC_APERTURE10_CNTL__BYPASS_MODE_MASK 0x00000010L
//VCN_MES_DC_APERTURE11_BASE
#define VCN_MES_DC_APERTURE11_BASE__BASE__SHIFT 0x0
#define VCN_MES_DC_APERTURE11_BASE__BASE_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE11_MASK
#define VCN_MES_DC_APERTURE11_MASK__MASK__SHIFT 0x0
#define VCN_MES_DC_APERTURE11_MASK__MASK_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE11_CNTL
#define VCN_MES_DC_APERTURE11_CNTL__VMID__SHIFT 0x0
#define VCN_MES_DC_APERTURE11_CNTL__BYPASS_MODE__SHIFT 0x4
#define VCN_MES_DC_APERTURE11_CNTL__VMID_MASK 0x0000000FL
#define VCN_MES_DC_APERTURE11_CNTL__BYPASS_MODE_MASK 0x00000010L
//VCN_MES_DC_APERTURE12_BASE
#define VCN_MES_DC_APERTURE12_BASE__BASE__SHIFT 0x0
#define VCN_MES_DC_APERTURE12_BASE__BASE_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE12_MASK
#define VCN_MES_DC_APERTURE12_MASK__MASK__SHIFT 0x0
#define VCN_MES_DC_APERTURE12_MASK__MASK_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE12_CNTL
#define VCN_MES_DC_APERTURE12_CNTL__VMID__SHIFT 0x0
#define VCN_MES_DC_APERTURE12_CNTL__BYPASS_MODE__SHIFT 0x4
#define VCN_MES_DC_APERTURE12_CNTL__VMID_MASK 0x0000000FL
#define VCN_MES_DC_APERTURE12_CNTL__BYPASS_MODE_MASK 0x00000010L
//VCN_MES_DC_APERTURE13_BASE
#define VCN_MES_DC_APERTURE13_BASE__BASE__SHIFT 0x0
#define VCN_MES_DC_APERTURE13_BASE__BASE_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE13_MASK
#define VCN_MES_DC_APERTURE13_MASK__MASK__SHIFT 0x0
#define VCN_MES_DC_APERTURE13_MASK__MASK_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE13_CNTL
#define VCN_MES_DC_APERTURE13_CNTL__VMID__SHIFT 0x0
#define VCN_MES_DC_APERTURE13_CNTL__BYPASS_MODE__SHIFT 0x4
#define VCN_MES_DC_APERTURE13_CNTL__VMID_MASK 0x0000000FL
#define VCN_MES_DC_APERTURE13_CNTL__BYPASS_MODE_MASK 0x00000010L
//VCN_MES_DC_APERTURE14_BASE
#define VCN_MES_DC_APERTURE14_BASE__BASE__SHIFT 0x0
#define VCN_MES_DC_APERTURE14_BASE__BASE_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE14_MASK
#define VCN_MES_DC_APERTURE14_MASK__MASK__SHIFT 0x0
#define VCN_MES_DC_APERTURE14_MASK__MASK_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE14_CNTL
#define VCN_MES_DC_APERTURE14_CNTL__VMID__SHIFT 0x0
#define VCN_MES_DC_APERTURE14_CNTL__BYPASS_MODE__SHIFT 0x4
#define VCN_MES_DC_APERTURE14_CNTL__VMID_MASK 0x0000000FL
#define VCN_MES_DC_APERTURE14_CNTL__BYPASS_MODE_MASK 0x00000010L
//VCN_MES_DC_APERTURE15_BASE
#define VCN_MES_DC_APERTURE15_BASE__BASE__SHIFT 0x0
#define VCN_MES_DC_APERTURE15_BASE__BASE_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE15_MASK
#define VCN_MES_DC_APERTURE15_MASK__MASK__SHIFT 0x0
#define VCN_MES_DC_APERTURE15_MASK__MASK_MASK 0xFFFFFFFFL
//VCN_MES_DC_APERTURE15_CNTL
#define VCN_MES_DC_APERTURE15_CNTL__VMID__SHIFT 0x0
#define VCN_MES_DC_APERTURE15_CNTL__BYPASS_MODE__SHIFT 0x4
#define VCN_MES_DC_APERTURE15_CNTL__VMID_MASK 0x0000000FL
#define VCN_MES_DC_APERTURE15_CNTL__BYPASS_MODE_MASK 0x00000010L
//VCN_HYP_ME1_PIPE0_VMID_CNTL
#define VCN_HYP_ME1_PIPE0_VMID_CNTL__VMID_ALLOWED_MASK__SHIFT 0x0
#define VCN_HYP_ME1_PIPE0_VMID_CNTL__VMID_DEFAULT__SHIFT 0x10
#define VCN_HYP_ME1_PIPE0_VMID_CNTL__VMID_ALLOWED_MASK_MASK 0x0000FFFFL
#define VCN_HYP_ME1_PIPE0_VMID_CNTL__VMID_DEFAULT_MASK 0x000F0000L
//VCN_HYP_ME1_PIPE1_VMID_CNTL
#define VCN_HYP_ME1_PIPE1_VMID_CNTL__VMID_ALLOWED_MASK__SHIFT 0x0
#define VCN_HYP_ME1_PIPE1_VMID_CNTL__VMID_DEFAULT__SHIFT 0x10
#define VCN_HYP_ME1_PIPE1_VMID_CNTL__VMID_ALLOWED_MASK_MASK 0x0000FFFFL
#define VCN_HYP_ME1_PIPE1_VMID_CNTL__VMID_DEFAULT_MASK 0x000F0000L
//VCN_MES_IC_BASE_LO
#define VCN_MES_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc
#define VCN_MES_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L
//VCN_MES_MIBASE_LO
#define VCN_MES_MIBASE_LO__IC_BASE_LO__SHIFT 0xc
#define VCN_MES_MIBASE_LO__IC_BASE_LO_MASK 0xFFFFF000L
//VCN_MES_IC_BASE_HI
#define VCN_MES_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0
#define VCN_MES_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL
//VCN_MES_MIBASE_HI
#define VCN_MES_MIBASE_HI__IC_BASE_HI__SHIFT 0x0
#define VCN_MES_MIBASE_HI__IC_BASE_HI_MASK 0x0000FFFFL
//VCN_MES_IC_BASE_CNTL
#define VCN_MES_IC_BASE_CNTL__VMID__SHIFT 0x0
#define VCN_MES_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17
#define VCN_MES_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18
#define VCN_MES_IC_BASE_CNTL__VMID_MASK 0x0000000FL
#define VCN_MES_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L
#define VCN_MES_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L
//VCN_MES_DC_BASE_LO
#define VCN_MES_DC_BASE_LO__DC_BASE_LO__SHIFT 0x10
#define VCN_MES_DC_BASE_LO__DC_BASE_LO_MASK 0xFFFF0000L
//VCN_MES_MDBASE_LO
#define VCN_MES_MDBASE_LO__BASE_LO__SHIFT 0x10
#define VCN_MES_MDBASE_LO__BASE_LO_MASK 0xFFFF0000L
//VCN_MES_DC_BASE_HI
#define VCN_MES_DC_BASE_HI__DC_BASE_HI__SHIFT 0x0
#define VCN_MES_DC_BASE_HI__DC_BASE_HI_MASK 0x0000FFFFL
//VCN_MES_MDBASE_HI
#define VCN_MES_MDBASE_HI__BASE_HI__SHIFT 0x0
#define VCN_MES_MDBASE_HI__BASE_HI_MASK 0x0000FFFFL
//VCN_MES_MIBOUND_LO
#define VCN_MES_MIBOUND_LO__BOUND_LO__SHIFT 0x0
#define VCN_MES_MIBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL
//VCN_MES_MIBOUND_HI
#define VCN_MES_MIBOUND_HI__BOUND_HI__SHIFT 0x0
#define VCN_MES_MIBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL
//VCN_MES_MDBOUND_LO
#define VCN_MES_MDBOUND_LO__BOUND_LO__SHIFT 0x0
#define VCN_MES_MDBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL
//VCN_MES_MDBOUND_HI
#define VCN_MES_MDBOUND_HI__BOUND_HI__SHIFT 0x0
#define VCN_MES_MDBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL
#endif

1797
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_offset.h Normal file
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File diff suppressed because it is too large Load Diff

8614
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h Normal file
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File diff suppressed because it is too large Load Diff

1553
drivers/gpu/drm/amd/include/asic_reg/vpe/vpe_6_1_0_offset.h Normal file
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File diff suppressed because it is too large Load Diff

4393
drivers/gpu/drm/amd/include/asic_reg/vpe/vpe_6_1_0_sh_mask.h Normal file
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File diff suppressed because it is too large Load Diff

40
drivers/gpu/drm/amd/include/ivsrcid/vpe/irqsrcs_vpe_6_1.h Normal file
View File

@@ -0,0 +1,40 @@
/*
* Copyright 2022 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __IRQSRCS_VPE_6_1_H__
#define __IRQSRCS_VPE_6_1_H__
#define VPE_6_1_SRCID__VPE_ATOMIC_RTN_DONE 0 // 0x0 VPE atomic*_rtn ops complete
#define VPE_6_1_SRCID__VPE_TRAP 1 // 0x1 Trap
#define VPE_6_1_SRCID__VPE_SRBMWRITE 2 // 0x2 SRBM write protection
#define VPE_6_1_SRCID__VPE_CTXEMPTY 3 // 0x3 Context Empty
#define VPE_6_1_SRCID__VPE_PREEMPT 4 // 0x4 Preemption
#define VPE_6_1_SRCID__VPE_QUEUE_HANG 5 // 0x5 Queue hang or Command timeout
#define VPE_6_1_SRCID__VPE_ATOMIC_TIMEOUT 6 // 0x6 Atomic CMPSWAP loop timeout
#define VPE_6_1_SRCID__VPE_POLL_TIMEOUT 7 // 0x7 SRBM read poll timeout
#define VPE_6_1_SRCID__VPE_VM_HOLE 8 // 0x8 Address in VM hole
#define VPE_6_1_SRCID__VPE_NACK_GEN_ERR 9 // 0x9 MMHUB return general error (nack = 3)
#define VPE_6_1_SRCID__VPE_NACK_PRT 10 // 0xA MMHUB return PRT (nack = 2)
#define VPE_6_1_SRCID__VPE_DOORBELL_INVALID 11 // 0xB Doorbell BE invalid
#define VPE_6_1_SRCID__VPE_IB_PREEMPT 12 // 0xC IB preemption
#endif

16
drivers/gpu/drm/amd/include/kgd_kfd_interface.h
View File

@@ -57,20 +57,6 @@ struct kfd_vm_fault_info {
bool prot_exec;
};
struct kfd_cu_info {
uint32_t num_shader_engines;
uint32_t num_shader_arrays_per_engine;
uint32_t num_cu_per_sh;
uint32_t cu_active_number;
uint32_t cu_ao_mask;
uint32_t simd_per_cu;
uint32_t max_waves_per_simd;
uint32_t wave_front_size;
uint32_t max_scratch_slots_per_cu;
uint32_t lds_size;
uint32_t cu_bitmap[AMDGPU_MAX_GC_INSTANCES][4][4];
};
/* For getting GPU local memory information from KGD */
struct kfd_local_mem_info {
uint64_t local_mem_size_private;
@@ -123,7 +109,7 @@ struct kgd2kfd_shared_resources {
uint32_t num_queue_per_pipe;
/* Bit n == 1 means Queue n is available for KFD */
DECLARE_BITMAP(cp_queue_bitmap, KGD_MAX_QUEUES);
DECLARE_BITMAP(cp_queue_bitmap, AMDGPU_MAX_QUEUES);
/* SDMA doorbell assignments (SOC15 and later chips only). Only
* specific doorbells are routed to each SDMA engine. Others

165
drivers/gpu/drm/amd/include/kgd_pp_interface.h
View File

@@ -28,6 +28,7 @@ extern const struct amdgpu_ip_block_version pp_smu_ip_block;
extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
extern const struct amdgpu_ip_block_version smu_v13_0_ip_block;
extern const struct amdgpu_ip_block_version smu_v14_0_ip_block;
enum smu_event_type {
SMU_EVENT_RESET_COMPLETE = 0,
@@ -113,6 +114,11 @@ enum pp_clock_type {
OD_RANGE,
OD_VDDGFX_OFFSET,
OD_CCLK,
OD_FAN_CURVE,
OD_ACOUSTIC_LIMIT,
OD_ACOUSTIC_TARGET,
OD_FAN_TARGET_TEMPERATURE,
OD_FAN_MINIMUM_PWM,
};
enum amd_pp_sensors {
@@ -186,7 +192,12 @@ enum PP_OD_DPM_TABLE_COMMAND {
PP_OD_EDIT_VDDC_CURVE,
PP_OD_RESTORE_DEFAULT_TABLE,
PP_OD_COMMIT_DPM_TABLE,
PP_OD_EDIT_VDDGFX_OFFSET
PP_OD_EDIT_VDDGFX_OFFSET,
PP_OD_EDIT_FAN_CURVE,
PP_OD_EDIT_ACOUSTIC_LIMIT,
PP_OD_EDIT_ACOUSTIC_TARGET,
PP_OD_EDIT_FAN_TARGET_TEMPERATURE,
PP_OD_EDIT_FAN_MINIMUM_PWM,
};
struct pp_states_info {
@@ -255,6 +266,14 @@ enum pp_power_type
PP_PWR_TYPE_FAST,
};
enum pp_xgmi_plpd_mode {
XGMI_PLPD_NONE = -1,
XGMI_PLPD_DISALLOW,
XGMI_PLPD_DEFAULT,
XGMI_PLPD_OPTIMIZED,
XGMI_PLPD_COUNT,
};
#define PP_GROUP_MASK 0xF0000000
#define PP_GROUP_SHIFT 28
@@ -295,6 +314,10 @@ enum pp_power_type
#define XGMI_MODE_PSTATE_D0 1
#define NUM_HBM_INSTANCES 4
#define NUM_XGMI_LINKS 8
#define MAX_GFX_CLKS 8
#define MAX_CLKS 4
#define NUM_VCN 4
struct seq_file;
enum amd_pp_clock_type;
@@ -678,6 +701,78 @@ struct gpu_metrics_v1_3 {
uint64_t indep_throttle_status;
};
struct gpu_metrics_v1_4 {
struct metrics_table_header common_header;
/* Temperature (Celsius) */
uint16_t temperature_hotspot;
uint16_t temperature_mem;
uint16_t temperature_vrsoc;
/* Power (Watts) */
uint16_t curr_socket_power;
/* Utilization (%) */
uint16_t average_gfx_activity;
uint16_t average_umc_activity; // memory controller
uint16_t vcn_activity[NUM_VCN];
/* Energy (15.259uJ (2^-16) units) */
uint64_t energy_accumulator;
/* Driver attached timestamp (in ns) */
uint64_t system_clock_counter;
/* Throttle status */
uint32_t throttle_status;
/* Clock Lock Status. Each bit corresponds to clock instance */
uint32_t gfxclk_lock_status;
/* Link width (number of lanes) and speed (in 0.1 GT/s) */
uint16_t pcie_link_width;
uint16_t pcie_link_speed;
/* XGMI bus width and bitrate (in Gbps) */
uint16_t xgmi_link_width;
uint16_t xgmi_link_speed;
/* Utilization Accumulated (%) */
uint32_t gfx_activity_acc;
uint32_t mem_activity_acc;
/*PCIE accumulated bandwidth (GB/sec) */
uint64_t pcie_bandwidth_acc;
/*PCIE instantaneous bandwidth (GB/sec) */
uint64_t pcie_bandwidth_inst;
/* PCIE L0 to recovery state transition accumulated count */
uint64_t pcie_l0_to_recov_count_acc;
/* PCIE replay accumulated count */
uint64_t pcie_replay_count_acc;
/* PCIE replay rollover accumulated count */
uint64_t pcie_replay_rover_count_acc;
/* XGMI accumulated data transfer size(KiloBytes) */
uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS];
uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS];
/* PMFW attached timestamp (10ns resolution) */
uint64_t firmware_timestamp;
/* Current clocks (Mhz) */
uint16_t current_gfxclk[MAX_GFX_CLKS];
uint16_t current_socclk[MAX_CLKS];
uint16_t current_vclk0[MAX_CLKS];
uint16_t current_dclk0[MAX_CLKS];
uint16_t current_uclk;
uint16_t padding;
};
/*
* gpu_metrics_v2_0 is not recommended as it's not naturally aligned.
* Use gpu_metrics_v2_1 or later instead.
@@ -962,4 +1057,72 @@ struct gpu_metrics_v2_4 {
uint16_t average_soc_current;
uint16_t average_gfx_current;
};
struct gpu_metrics_v3_0 {
struct metrics_table_header common_header;
/* Temperature */
/* gfx temperature on APUs */
uint16_t temperature_gfx;
/* soc temperature on APUs */
uint16_t temperature_soc;
/* CPU core temperature on APUs */
uint16_t temperature_core[16];
/* skin temperature on APUs */
uint16_t temperature_skin;
/* Utilization */
/* time filtered GFX busy % [0-100] */
uint16_t average_gfx_activity;
/* time filtered VCN busy % [0-100] */
uint16_t average_vcn_activity;
/* time filtered IPU per-column busy % [0-100] */
uint16_t average_ipu_activity[8];
/* time filtered per-core C0 residency % [0-100]*/
uint16_t average_core_c0_activity[16];
/* time filtered DRAM read bandwidth [GB/sec] */
uint16_t average_dram_reads;
/* time filtered DRAM write bandwidth [GB/sec] */
uint16_t average_dram_writes;
/* Driver attached timestamp (in ns) */
uint64_t system_clock_counter;
/* Power/Energy */
/* average dGPU + APU power on A + A platform */
uint32_t average_socket_power;
/* average IPU power [W] */
uint16_t average_ipu_power;
/* average APU power [W] */
uint32_t average_apu_power;
/* average dGPU power [W] */
uint32_t average_dgpu_power;
/* sum of core power across all cores in the socket [W] */
uint32_t average_core_power;
/* calculated core power [W] */
uint16_t core_power[16];
/* maximum IRM defined STAPM power limit [W] */
uint16_t stapm_power_limit;
/* time filtered STAPM power limit [W] */
uint16_t current_stapm_power_limit;
/* Average clocks */
uint16_t average_gfxclk_frequency;
uint16_t average_socclk_frequency;
uint16_t average_vpeclk_frequency;
uint16_t average_ipuclk_frequency;
uint16_t average_fclk_frequency;
uint16_t average_vclk_frequency;
/* Current clocks */
/* target core frequency */
uint16_t current_coreclk[16];
/* CCLK frequency limit enforced on classic cores [MHz] */
uint16_t current_core_maxfreq;
/* GFXCLK frequency limit enforced on GFX [MHz] */
uint16_t current_gfx_maxfreq;
/* Metrics table alpha filter time constant [us] */
uint32_t time_filter_alphavalue;
};
#endif

4
drivers/gpu/drm/amd/include/pptable.h
View File

@@ -78,7 +78,7 @@ typedef struct _ATOM_PPLIB_THERMALCONTROLLER
typedef struct _ATOM_PPLIB_STATE
{
UCHAR ucNonClockStateIndex;
UCHAR ucClockStateIndices[1]; // variable-sized
UCHAR ucClockStateIndices[]; // variable-sized
} ATOM_PPLIB_STATE;
@@ -473,7 +473,7 @@ typedef struct _ATOM_PPLIB_STATE_V2
/**
* Driver will read the first ucNumDPMLevels in this array
*/
UCHAR clockInfoIndex[1];
UCHAR clockInfoIndex[];
} ATOM_PPLIB_STATE_V2;
typedef struct _StateArray{

1
drivers/gpu/drm/amd/include/soc15_hw_ip.h
View File

@@ -43,6 +43,7 @@
#define DAZ_HWID 274
#define SDPMUX_HWID 19
#define NTB_HWID 20
#define VPE_HWID 21
#define IOHC_HWID 24
#define L2IMU_HWID 28
#define VCE_HWID 32

2
drivers/gpu/drm/amd/include/soc15_ih_clientid.h
View File

@@ -95,10 +95,12 @@ enum soc21_ih_clientid {
SOC21_IH_CLIENTID_VCN1 = 0x0e,
SOC21_IH_CLIENTID_THM = 0x0f,
SOC21_IH_CLIENTID_VCN = 0x10,
SOC21_IH_CLIENTID_VPE1 = 0x11,
SOC21_IH_CLIENTID_VMC = 0x12,
SOC21_IH_CLIENTID_GRBM_CP = 0x14,
SOC21_IH_CLIENTID_ROM_SMUIO = 0x16,
SOC21_IH_CLIENTID_DF = 0x17,
SOC21_IH_CLIENTID_VPE = 0x18,
SOC21_IH_CLIENTID_PWR = 0x19,
SOC21_IH_CLIENTID_LSDMA = 0x1a,
SOC21_IH_CLIENTID_MP0 = 0x1e,

437
drivers/gpu/drm/amd/include/umsch_mm_4_0_api_def.h Normal file
View File

@@ -0,0 +1,437 @@
/* SPDX-License-Identifier: MIT */
/*
* Copyright 2023 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __UMSCH_MM_API_DEF_H__
#define __UMSCH_MM_API_DEF_H__
#pragma once
#pragma pack(push, 4)
#define UMSCH_API_VERSION 1
/*
* Driver submits one API(cmd) as a single Frame and this command size is same for all API
* to ease the debugging and parsing of ring buffer.
*/
enum { API_FRAME_SIZE_IN_DWORDS = 64 };
/*
* To avoid command in scheduler context to be overwritten whenever multiple interrupts come in,
* this creates another queue.
*/
enum { API_NUMBER_OF_COMMAND_MAX = 32 };
enum { UMSCH_INSTANCE_DB_OFFSET_MAX = 16 };
enum UMSCH_API_TYPE {
UMSCH_API_TYPE_SCHEDULER = 1,
UMSCH_API_TYPE_MAX
};
enum UMSCH_MS_LOG_CONTEXT_STATE {
UMSCH_LOG_CONTEXT_STATE_IDLE = 0,
UMSCH_LOG_CONTEXT_STATE_RUNNING = 1,
UMSCH_LOG_CONTEXT_STATE_READY = 2,
UMSCH_LOG_CONTEXT_STATE_READY_STANDBY = 3,
UMSCH_LOG_CONTEXT_STATE_INVALID = 0xF,
};
enum UMSCH_MS_LOG_OPERATION {
UMSCH_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0,
UMSCH_LOG_OPERATION_QUEUE_NEW_WORK = 1,
UMSCH_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT = 2,
UMSCH_LOG_OPERATION_QUEUE_NO_MORE_WORK = 3,
UMSCH_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT = 4,
UMSCH_LOG_OPERATION_QUEUE_INVALID = 0xF,
};
struct UMSCH_INSTANCE_DB_OFFSET {
uint32_t instance_index;
uint32_t doorbell_offset;
};
struct UMSCH_LOG_CONTEXT_STATE_CHANGE {
uint64_t h_context;
enum UMSCH_MS_LOG_CONTEXT_STATE new_context_state;
};
struct UMSCH_LOG_QUEUE_NEW_WORK {
uint64_t h_queue;
uint64_t reserved;
};
struct UMSCH_LOG_QUEUE_UNWAIT_SYNC_OBJECT {
uint64_t h_queue;
uint64_t h_sync_object;
};
struct UMSCH_LOG_QUEUE_NO_MORE_WORK {
uint64_t h_queue;
uint64_t reserved;
};
struct UMSCH_LOG_QUEUE_WAIT_SYNC_OBJECT {
uint64_t h_queue;
uint64_t h_sync_object;
};
struct UMSCH_LOG_ENTRY_HEADER {
uint32_t first_free_entry_index;
uint32_t wraparound_count;
uint64_t number_of_entries;
uint64_t reserved[2];
};
struct UMSCH_LOG_ENTRY_DATA {
uint64_t gpu_time_stamp;
uint32_t operation_type; /* operation_type is of UMSCH_LOG_OPERATION type */
uint32_t reserved_operation_type_bits;
union {
struct UMSCH_LOG_CONTEXT_STATE_CHANGE context_state_change;
struct UMSCH_LOG_QUEUE_NEW_WORK queue_new_work;
struct UMSCH_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object;
struct UMSCH_LOG_QUEUE_NO_MORE_WORK queue_no_more_work;
struct UMSCH_LOG_QUEUE_WAIT_SYNC_OBJECT queue_wait_sync_object;
uint64_t all[2];
};
};
struct UMSCH_LOG_BUFFER {
struct UMSCH_LOG_ENTRY_HEADER header;
struct UMSCH_LOG_ENTRY_DATA entries[1];
};
enum UMSCH_API_OPCODE {
UMSCH_API_SET_HW_RSRC = 0x00,
UMSCH_API_SET_SCHEDULING_CONFIG = 0x1,
UMSCH_API_ADD_QUEUE = 0x2,
UMSCH_API_REMOVE_QUEUE = 0x3,
UMSCH_API_PERFORM_YIELD = 0x4,
UMSCH_API_SUSPEND = 0x5,
UMSCH_API_RESUME = 0x6,
UMSCH_API_RESET = 0x7,
UMSCH_API_SET_LOG_BUFFER = 0x8,
UMSCH_API_CHANGE_CONTEXT_PRIORITY = 0x9,
UMSCH_API_QUERY_SCHEDULER_STATUS = 0xA,
UMSCH_API_UPDATE_AFFINITY = 0xB,
UMSCH_API_MAX = 0xFF
};
union UMSCH_API_HEADER {
struct {
uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */
uint32_t opcode : 8;
uint32_t dwsize : 8;
uint32_t reserved : 12;
};
uint32_t u32All;
};
enum UMSCH_AMD_PRIORITY_LEVEL {
AMD_PRIORITY_LEVEL_IDLE = 0,
AMD_PRIORITY_LEVEL_NORMAL = 1,
AMD_PRIORITY_LEVEL_FOCUS = 2,
AMD_PRIORITY_LEVEL_REALTIME = 3,
AMD_PRIORITY_NUM_LEVELS
};
enum UMSCH_ENGINE_TYPE {
UMSCH_ENGINE_TYPE_VCN0 = 0,
UMSCH_ENGINE_TYPE_VCN1 = 1,
UMSCH_ENGINE_TYPE_VCN = 2,
UMSCH_ENGINE_TYPE_VPE = 3,
UMSCH_ENGINE_TYPE_MAX
};
#define AFFINITY_DISABLE 0
#define AFFINITY_ENABLE 1
#define AFFINITY_MAX 2
union UMSCH_AFFINITY {
struct {
unsigned int vcn0Affinity : 2; /* enable 1 disable 0 */
unsigned int vcn1Affinity : 2;
unsigned int reserved : 28;
};
unsigned int u32All;
};
struct UMSCH_API_STATUS {
uint64_t api_completion_fence_addr;
uint32_t api_completion_fence_value;
};
enum { MAX_VCN0_INSTANCES = 1 };
enum { MAX_VCN1_INSTANCES = 1 };
enum { MAX_VCN_INSTANCES = 2 };
enum { MAX_VPE_INSTANCES = 1 };
enum { MAX_VCN_QUEUES = 4 };
enum { MAX_VPE_QUEUES = 8 };
enum { MAX_QUEUES_IN_A_CONTEXT = 1 };
enum { UMSCH_MAX_HWIP_SEGMENT = 8 };
enum VM_HUB_TYPE {
VM_HUB_TYPE_GC = 0,
VM_HUB_TYPE_MM = 1,
VM_HUB_TYPE_MAX,
};
enum { VMID_INVALID = 0xffff };
enum { MAX_VMID_MMHUB = 16 };
union UMSCHAPI__SET_HW_RESOURCES {
struct {
union UMSCH_API_HEADER header;
uint32_t vmid_mask_mm_vcn;
uint32_t vmid_mask_mm_vpe;
uint32_t collaboration_mask_vpe;
uint32_t engine_mask;
uint32_t logging_vmid;
uint32_t vcn0_hqd_mask[MAX_VCN0_INSTANCES];
uint32_t vcn1_hqd_mask[MAX_VCN1_INSTANCES];
uint32_t vcn_hqd_mask[MAX_VCN_INSTANCES];
uint32_t vpe_hqd_mask[MAX_VPE_INSTANCES];
uint64_t g_sch_ctx_gpu_mc_ptr;
uint32_t mmhub_base[UMSCH_MAX_HWIP_SEGMENT];
uint32_t mmhub_version;
uint32_t osssys_base[UMSCH_MAX_HWIP_SEGMENT];
uint32_t osssys_version;
uint32_t vcn_version;
uint32_t vpe_version;
struct UMSCH_API_STATUS api_status;
union {
struct {
uint32_t disable_reset : 1;
uint32_t disable_umsch_log : 1;
uint32_t enable_level_process_quantum_check : 1;
uint32_t is_vcn0_enabled : 1;
uint32_t is_vcn1_enabled : 1;
uint32_t reserved : 27;
};
uint32_t uint32_all;
};
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
static_assert(sizeof(union UMSCHAPI__SET_HW_RESOURCES) <= API_FRAME_SIZE_IN_DWORDS * sizeof(uint32_t),
"size of UMSCHAPI__SET_HW_RESOURCES must be less than 256 bytes");
union UMSCHAPI__SET_SCHEDULING_CONFIG {
struct {
union UMSCH_API_HEADER header;
/*
* Grace period when preempting another priority band for this priority band.
* The value for idle priority band is ignored, as it never preempts other bands.
*/
uint64_t grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS];
/* Default quantum for scheduling across processes within a priority band. */
uint64_t process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS];
/* Default grace period for processes that preempt each other within a priority band. */
uint64_t process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS];
/*
* For normal level this field specifies the target GPU percentage in situations
* when it's starved by the high level. Valid values are between 0 and 50,
* with the default being 10.
*/
uint32_t normal_yield_percent;
struct UMSCH_API_STATUS api_status;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union UMSCHAPI__ADD_QUEUE {
struct {
union UMSCH_API_HEADER header;
uint32_t process_id;
uint64_t page_table_base_addr;
uint64_t process_va_start;
uint64_t process_va_end;
uint64_t process_quantum;
uint64_t process_csa_addr;
uint64_t context_quantum;
uint64_t context_csa_addr;
uint32_t inprocess_context_priority;
enum UMSCH_AMD_PRIORITY_LEVEL context_global_priority_level;
uint32_t doorbell_offset_0;
uint32_t doorbell_offset_1;
union UMSCH_AFFINITY affinity;
uint64_t mqd_addr;
uint64_t h_context;
uint64_t h_queue;
enum UMSCH_ENGINE_TYPE engine_type;
uint32_t vm_context_cntl;
struct {
uint32_t is_context_suspended : 1;
uint32_t reserved : 31;
};
struct UMSCH_API_STATUS api_status;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union UMSCHAPI__REMOVE_QUEUE {
struct {
union UMSCH_API_HEADER header;
uint32_t doorbell_offset_0;
uint32_t doorbell_offset_1;
uint64_t context_csa_addr;
struct UMSCH_API_STATUS api_status;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union UMSCHAPI__PERFORM_YIELD {
struct {
union UMSCH_API_HEADER header;
uint32_t dummy;
struct UMSCH_API_STATUS api_status;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union UMSCHAPI__SUSPEND {
struct {
union UMSCH_API_HEADER header;
uint64_t context_csa_addr;
uint64_t suspend_fence_addr;
uint32_t suspend_fence_value;
struct UMSCH_API_STATUS api_status;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
enum UMSCH_RESUME_OPTION {
CONTEXT_RESUME = 0,
ENGINE_SCHEDULE_RESUME = 1,
};
union UMSCHAPI__RESUME {
struct {
union UMSCH_API_HEADER header;
enum UMSCH_RESUME_OPTION resume_option;
uint64_t context_csa_addr; /* valid only for UMSCH_SWIP_CONTEXT_RESUME */
enum UMSCH_ENGINE_TYPE engine_type;
struct UMSCH_API_STATUS api_status;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
enum UMSCH_RESET_OPTION {
HANG_DETECT_AND_RESET = 0,
HANG_DETECT_ONLY = 1,
};
union UMSCHAPI__RESET {
struct {
union UMSCH_API_HEADER header;
enum UMSCH_RESET_OPTION reset_option;
uint64_t doorbell_offset_addr;
enum UMSCH_ENGINE_TYPE engine_type;
struct UMSCH_API_STATUS api_status;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union UMSCHAPI__SET_LOGGING_BUFFER {
struct {
union UMSCH_API_HEADER header;
/* There are separate log buffers for each queue type */
enum UMSCH_ENGINE_TYPE log_type;
/* Log buffer GPU Address */
uint64_t logging_buffer_addr;
/* Number of entries in the log buffer */
uint32_t number_of_entries;
/* Entry index at which CPU interrupt needs to be signalled */
uint32_t interrupt_entry;
struct UMSCH_API_STATUS api_status;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union UMSCHAPI__UPDATE_AFFINITY {
struct {
union UMSCH_API_HEADER header;
union UMSCH_AFFINITY affinity;
uint64_t context_csa_addr;
struct UMSCH_API_STATUS api_status;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union UMSCHAPI__CHANGE_CONTEXT_PRIORITY_LEVEL {
struct {
union UMSCH_API_HEADER header;
uint32_t inprocess_context_priority;
enum UMSCH_AMD_PRIORITY_LEVEL context_global_priority_level;
uint64_t context_quantum;
uint64_t context_csa_addr;
struct UMSCH_API_STATUS api_status;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
union UMSCHAPI__QUERY_UMSCH_STATUS {
struct {
union UMSCH_API_HEADER header;
bool umsch_mm_healthy; /* 0 - not healthy, 1 - healthy */
struct UMSCH_API_STATUS api_status;
};
uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
};
#pragma pack(pop)
#endif