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drm/amdgpu: add helper to query rlcg reg access flag

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Query rlc indirect register access approach specified
by sriov host driver per ip blocks

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Zhou, Peng Ju <PengJu.Zhou@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hawking Zhang
2022-01-18 16:04:02 +08:00
committed by Alex Deucher
parent 5bb1465fbd
commit 29dbcac82f
2 changed files with 43 additions and 0 deletions
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35
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
View File

@@ -820,3 +820,38 @@ void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
}
}
}
bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, u32 acc_flags,
u32 hwip, bool write, u32 *rlcg_flag)
{
bool ret = false;
switch (hwip) {
case GC_HWIP:
if (amdgpu_sriov_reg_indirect_gc(adev)) {
*rlcg_flag =
write ? AMDGPU_RLCG_GC_WRITE : AMDGPU_RLCG_GC_READ;
ret = true;
/* only in new version, AMDGPU_REGS_NO_KIQ and
* AMDGPU_REGS_RLC are enabled simultaneously */
} else if ((acc_flags & AMDGPU_REGS_RLC) &&
!(acc_flags & AMDGPU_REGS_NO_KIQ)) {
*rlcg_flag = AMDGPU_RLCG_GC_WRITE_LEGACY;
ret = true;
}
break;
case MMHUB_HWIP:
if (amdgpu_sriov_reg_indirect_mmhub(adev) &&
(acc_flags & AMDGPU_REGS_RLC) && write) {
*rlcg_flag = AMDGPU_RLCG_MMHUB_WRITE;
ret = true;
}
break;
default:
dev_err(adev->dev,
"indirect registers access through rlcg is not supported\n");
ret = false;
break;
}
return ret;
}