mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
synced 2026-04-23 05:56:14 -04:00
drm/amd/display: clean up some inconsistent indenting
No functional modification involved. drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn321/dcn321_fpu.c:556 dcn321_update_bw_bounding_box_fpu() warn: inconsistent indenting. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5304 Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jiapeng Chong
committed by
Alex Deucher
Alex Deucher
parent
2c4993bf88
commit
3a10a44a3e
@@ -553,148 +553,148 @@ void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_p
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dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
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/* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */
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if (dc->debug.use_legacy_soc_bb_mechanism) {
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unsigned int i = 0, j = 0, num_states = 0;
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if (dc->debug.use_legacy_soc_bb_mechanism) {
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unsigned int i = 0, j = 0, num_states = 0;
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unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
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unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
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unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
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unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
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unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
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unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
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unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
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unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
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unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564};
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unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0;
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unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
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unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564};
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unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0;
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unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
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for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
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if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
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max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
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if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
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max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
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if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
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max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
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if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
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max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
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}
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if (!max_dcfclk_mhz)
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max_dcfclk_mhz = dcn3_21_soc.clock_limits[0].dcfclk_mhz;
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if (!max_dispclk_mhz)
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max_dispclk_mhz = dcn3_21_soc.clock_limits[0].dispclk_mhz;
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if (!max_dppclk_mhz)
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max_dppclk_mhz = dcn3_21_soc.clock_limits[0].dppclk_mhz;
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if (!max_phyclk_mhz)
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max_phyclk_mhz = dcn3_21_soc.clock_limits[0].phyclk_mhz;
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for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
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if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
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max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
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if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
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max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
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if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
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max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
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if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
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max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
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}
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if (!max_dcfclk_mhz)
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max_dcfclk_mhz = dcn3_21_soc.clock_limits[0].dcfclk_mhz;
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if (!max_dispclk_mhz)
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max_dispclk_mhz = dcn3_21_soc.clock_limits[0].dispclk_mhz;
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if (!max_dppclk_mhz)
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max_dppclk_mhz = dcn3_21_soc.clock_limits[0].dppclk_mhz;
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if (!max_phyclk_mhz)
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max_phyclk_mhz = dcn3_21_soc.clock_limits[0].phyclk_mhz;
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if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
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// If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
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dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
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num_dcfclk_sta_targets++;
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} else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
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// If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
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for (i = 0; i < num_dcfclk_sta_targets; i++) {
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if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
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dcfclk_sta_targets[i] = max_dcfclk_mhz;
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break;
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}
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}
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// Update size of array since we "removed" duplicates
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num_dcfclk_sta_targets = i + 1;
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}
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num_uclk_states = bw_params->clk_table.num_entries;
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// Calculate optimal dcfclk for each uclk
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for (i = 0; i < num_uclk_states; i++) {
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dcn321_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
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&optimal_dcfclk_for_uclk[i], NULL);
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if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
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optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
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}
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}
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// Calculate optimal uclk for each dcfclk sta target
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if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
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// If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
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dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
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num_dcfclk_sta_targets++;
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} else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
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// If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
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for (i = 0; i < num_dcfclk_sta_targets; i++) {
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for (j = 0; j < num_uclk_states; j++) {
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if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
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optimal_uclk_for_dcfclk_sta_targets[i] =
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bw_params->clk_table.entries[j].memclk_mhz * 16;
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break;
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}
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if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
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dcfclk_sta_targets[i] = max_dcfclk_mhz;
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break;
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}
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}
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i = 0;
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j = 0;
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// create the final dcfclk and uclk table
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while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
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if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
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dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
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dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
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} else {
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if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
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dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
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dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
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} else {
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j = num_uclk_states;
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}
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}
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}
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while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
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dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
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dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
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}
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while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
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optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
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dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
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dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
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}
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dcn3_21_soc.num_states = num_states;
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for (i = 0; i < dcn3_21_soc.num_states; i++) {
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dcn3_21_soc.clock_limits[i].state = i;
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dcn3_21_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
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dcn3_21_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
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/* Fill all states with max values of all these clocks */
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dcn3_21_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
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dcn3_21_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz;
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dcn3_21_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz;
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dcn3_21_soc.clock_limits[i].dscclk_mhz = max_dispclk_mhz / 3;
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/* Populate from bw_params for DTBCLK, SOCCLK */
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if (i > 0) {
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if (!bw_params->clk_table.entries[i].dtbclk_mhz) {
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dcn3_21_soc.clock_limits[i].dtbclk_mhz = dcn3_21_soc.clock_limits[i-1].dtbclk_mhz;
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} else {
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dcn3_21_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
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}
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} else if (bw_params->clk_table.entries[i].dtbclk_mhz) {
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dcn3_21_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
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}
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if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
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dcn3_21_soc.clock_limits[i].socclk_mhz = dcn3_21_soc.clock_limits[i-1].socclk_mhz;
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else
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dcn3_21_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
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if (!dram_speed_mts[i] && i > 0)
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dcn3_21_soc.clock_limits[i].dram_speed_mts = dcn3_21_soc.clock_limits[i-1].dram_speed_mts;
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else
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dcn3_21_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
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/* These clocks cannot come from bw_params, always fill from dcn3_21_soc[0] */
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/* PHYCLK_D18, PHYCLK_D32 */
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dcn3_21_soc.clock_limits[i].phyclk_d18_mhz = dcn3_21_soc.clock_limits[0].phyclk_d18_mhz;
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dcn3_21_soc.clock_limits[i].phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz;
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}
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} else {
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build_synthetic_soc_states(bw_params, dcn3_21_soc.clock_limits, &dcn3_21_soc.num_states);
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// Update size of array since we "removed" duplicates
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num_dcfclk_sta_targets = i + 1;
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}
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/* Re-init DML with updated bb */
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dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);
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if (dc->current_state)
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dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);
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num_uclk_states = bw_params->clk_table.num_entries;
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// Calculate optimal dcfclk for each uclk
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for (i = 0; i < num_uclk_states; i++) {
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dcn321_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
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&optimal_dcfclk_for_uclk[i], NULL);
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if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
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optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
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}
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}
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// Calculate optimal uclk for each dcfclk sta target
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for (i = 0; i < num_dcfclk_sta_targets; i++) {
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for (j = 0; j < num_uclk_states; j++) {
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if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
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optimal_uclk_for_dcfclk_sta_targets[i] =
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bw_params->clk_table.entries[j].memclk_mhz * 16;
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break;
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}
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}
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}
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i = 0;
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j = 0;
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// create the final dcfclk and uclk table
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while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
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if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
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dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
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dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
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} else {
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if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
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dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
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dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
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} else {
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j = num_uclk_states;
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}
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}
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}
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while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
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dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
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dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
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}
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while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
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optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
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dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
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dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
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}
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dcn3_21_soc.num_states = num_states;
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for (i = 0; i < dcn3_21_soc.num_states; i++) {
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dcn3_21_soc.clock_limits[i].state = i;
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dcn3_21_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
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dcn3_21_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
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/* Fill all states with max values of all these clocks */
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dcn3_21_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
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dcn3_21_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz;
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dcn3_21_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz;
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dcn3_21_soc.clock_limits[i].dscclk_mhz = max_dispclk_mhz / 3;
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/* Populate from bw_params for DTBCLK, SOCCLK */
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if (i > 0) {
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if (!bw_params->clk_table.entries[i].dtbclk_mhz) {
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dcn3_21_soc.clock_limits[i].dtbclk_mhz = dcn3_21_soc.clock_limits[i-1].dtbclk_mhz;
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} else {
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dcn3_21_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
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}
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} else if (bw_params->clk_table.entries[i].dtbclk_mhz) {
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dcn3_21_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
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}
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if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
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dcn3_21_soc.clock_limits[i].socclk_mhz = dcn3_21_soc.clock_limits[i-1].socclk_mhz;
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else
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dcn3_21_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
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if (!dram_speed_mts[i] && i > 0)
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dcn3_21_soc.clock_limits[i].dram_speed_mts = dcn3_21_soc.clock_limits[i-1].dram_speed_mts;
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else
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dcn3_21_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
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/* These clocks cannot come from bw_params, always fill from dcn3_21_soc[0] */
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/* PHYCLK_D18, PHYCLK_D32 */
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dcn3_21_soc.clock_limits[i].phyclk_d18_mhz = dcn3_21_soc.clock_limits[0].phyclk_d18_mhz;
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dcn3_21_soc.clock_limits[i].phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz;
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}
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} else {
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build_synthetic_soc_states(bw_params, dcn3_21_soc.clock_limits, &dcn3_21_soc.num_states);
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}
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/* Re-init DML with updated bb */
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dml_init_instance(&dc->dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);
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if (dc->current_state)
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dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_21_soc, &dcn3_21_ip, DML_PROJECT_DCN32);
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}
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