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drm/amd/display: Fix DP2 link training failure with RCO

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[Why]
When RCO is enabled for symclk32_le we get failures during
DP2 link traing compliance tests.

[How]
Break out symclk32_le RCO into a separate function that is
called for hpo when link is enabled/disabled.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Alan Liu <haoping.liu@amd.com>
Signed-off-by: Daniel Miess <daniel.miess@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Daniel Miess
2023-06-28 12:39:04 -04:00
committed by Alex Deucher
parent 2ad127ba4c
commit 3a87e25aaa
5 changed files with 50 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

49
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
View File

@@ -284,19 +284,11 @@ void dccg31_enable_symclk32_le(
/* select one of the PHYD32CLKs as the source for symclk32_le */
switch (hpo_le_inst) {
case 0:
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
SYMCLK32_LE0_GATE_DISABLE, 1,
SYMCLK32_ROOT_LE0_GATE_DISABLE, 1);
REG_UPDATE_2(SYMCLK32_LE_CNTL,
SYMCLK32_LE0_SRC_SEL, phyd32clk,
SYMCLK32_LE0_EN, 1);
break;
case 1:
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
SYMCLK32_LE1_GATE_DISABLE, 1,
SYMCLK32_ROOT_LE1_GATE_DISABLE, 1);
REG_UPDATE_2(SYMCLK32_LE_CNTL,
SYMCLK32_LE1_SRC_SEL, phyd32clk,
SYMCLK32_LE1_EN, 1);
@@ -319,19 +311,38 @@ void dccg31_disable_symclk32_le(
REG_UPDATE_2(SYMCLK32_LE_CNTL,
SYMCLK32_LE0_SRC_SEL, 0,
SYMCLK32_LE0_EN, 0);
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
SYMCLK32_LE0_GATE_DISABLE, 0,
SYMCLK32_ROOT_LE0_GATE_DISABLE, 0);
break;
case 1:
REG_UPDATE_2(SYMCLK32_LE_CNTL,
SYMCLK32_LE1_SRC_SEL, 0,
SYMCLK32_LE1_EN, 0);
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
SYMCLK32_LE1_GATE_DISABLE, 0,
SYMCLK32_ROOT_LE1_GATE_DISABLE, 0);
break;
default:
BREAK_TO_DEBUGGER();
return;
}
}
void dccg31_set_symclk32_le_root_clock_gating(
struct dccg *dccg,
int hpo_le_inst,
bool enable)
{
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
return;
switch (hpo_le_inst) {
case 0:
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
SYMCLK32_LE0_GATE_DISABLE, enable ? 1 : 0,
SYMCLK32_ROOT_LE0_GATE_DISABLE, enable ? 1 : 0);
break;
case 1:
REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL3,
SYMCLK32_LE1_GATE_DISABLE, enable ? 1 : 0,
SYMCLK32_ROOT_LE1_GATE_DISABLE, enable ? 1 : 0);
break;
default:
BREAK_TO_DEBUGGER();
@@ -660,10 +671,8 @@ void dccg31_init(struct dccg *dccg)
dccg31_disable_symclk32_se(dccg, 2);
dccg31_disable_symclk32_se(dccg, 3);
if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) {
dccg31_disable_symclk32_le(dccg, 0);
dccg31_disable_symclk32_le(dccg, 1);
}
dccg31_set_symclk32_le_root_clock_gating(dccg, 0, false);
dccg31_set_symclk32_le_root_clock_gating(dccg, 1, false);
if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {
dccg31_disable_dpstreamclk(dccg, 0);

5
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
View File

@@ -179,6 +179,11 @@ void dccg31_disable_symclk32_le(
struct dccg *dccg,
int hpo_le_inst);
void dccg31_set_symclk32_le_root_clock_gating(
struct dccg *dccg,
int hpo_le_inst,
bool enable);
void dccg31_set_physymclk(
struct dccg *dccg,
int phy_inst,