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drm/amd/display: Add timing generator count to resource pool.

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Use tg count in resource pool for further reference.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Yongqiang Sun
2018-01-05 13:53:06 -05:00
committed by Alex Deucher
parent 05133ac856
commit 3be1406a72
8 changed files with 12 additions and 4 deletions
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drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
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@@ -831,6 +831,7 @@ static bool construct(
/* TODO: Fill more data from GreenlandAsicCapability.cpp */
pool->base.pipe_count = res_cap.num_timing_generator;
pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
dc->caps.max_downscale_ratio = 200;