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drm/amdgpu: correct NBIO v7.11 programing

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Use v7.7 before, switch to v7.11 now.
Fix incorrect programing.

Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Lang Yu
2023-10-12 14:30:40 +08:00
committed by Alex Deucher
parent 2c1fe3c480
commit 4661482b9c
2 changed files with 33 additions and 32 deletions
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9
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_offset.h
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@@ -8187,9 +8187,9 @@
#define regBIF_BX0_PCIE_INDEX_BASE_IDX 5
#define regBIF_BX0_PCIE_DATA 0x800d
#define regBIF_BX0_PCIE_DATA_BASE_IDX 5
#define regBIF_BX0_PCIE_INDEX2 0xe
#define regBIF_BX0_PCIE_INDEX2 0x800e
#define regBIF_BX0_PCIE_INDEX2_BASE_IDX 0
#define regBIF_BX0_PCIE_DATA2 0xf
#define regBIF_BX0_PCIE_DATA2 0x800f
#define regBIF_BX0_PCIE_DATA2_BASE_IDX 0
#define regBIF_BX0_SBIOS_SCRATCH_0 0x8048
#define regBIF_BX0_SBIOS_SCRATCH_0_BASE_IDX 5
@@ -8678,7 +8678,10 @@
#define regBIF_BX_PF1_MM_DATA_BASE_IDX 0
#define regBIF_BX_PF1_MM_INDEX_HI 0x0006
#define regBIF_BX_PF1_MM_INDEX_HI_BASE_IDX 0
#define regBIF_BX_PF1_RSMU_INDEX 0x0000
#define regBIF_BX_PF1_RSMU_INDEX_BASE_IDX 1
#define regBIF_BX_PF1_RSMU_DATA 0x0001
#define regBIF_BX_PF1_RSMU_DATA_BASE_IDX 1
// addressBlock: nbio_nbif0_bif_bx_BIFDEC1:1
// base address: 0x0