mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
synced 2026-04-18 03:23:53 -04:00
Merge tag 'drm-next-2021-08-31-1' of git://anongit.freedesktop.org/drm/drm
Pull drm updates from Dave Airlie:
"Highlights:
- i915 has seen a lot of refactoring and uAPI cleanups due to a
change in the upstream direction going forward
This has all been audited with known userspace, but there may be
some pitfalls that were missed.
- i915 now uses common TTM to enable discrete memory on DG1/2 GPUs
- i915 enables Jasper and Elkhart Lake by default and has preliminary
XeHP/DG2 support
- amdgpu adds support for Cyan Skillfish
- lots of implicit fencing rules documented and fixed up in drivers
- msm now uses the core scheduler
- the irq midlayer has been removed for non-legacy drivers
- the sysfb code now works on more than x86.
Otherwise the usual smattering of stuff everywhere, panels, bridges,
refactorings.
Detailed summary:
core:
- extract i915 eDP backlight into core
- DP aux bus support
- drm_device.irq_enabled removed
- port drivers to native irq interfaces
- export gem shadow plane handling for vgem
- print proper driver name in framebuffer registration
- driver fixes for implicit fencing rules
- ARM fixed rate compression modifier added
- updated fb damage handling
- rmfb ioctl logging/docs
- drop drm_gem_object_put_locked
- define DRM_FORMAT_MAX_PLANES
- add gem fb vmap/vunmap helpers
- add lockdep_assert(once) helpers
- mark drm irq midlayer as legacy
- use offset adjusted bo mapping conversion
vgaarb:
- cleanups
fbdev:
- extend efifb handling to all arches
- div by 0 fixes for multiple drivers
udmabuf:
- add hugepage mapping support
dma-buf:
- non-dynamic exporter fixups
- document implicit fencing rules
amdgpu:
- Initial Cyan Skillfish support
- switch virtual DCE over to vkms based atomic
- VCN/JPEG power down fixes
- NAVI PCIE link handling fixes
- AMD HDMI freesync fixes
- Yellow Carp + Beige Goby fixes
- Clockgating/S0ix/SMU/EEPROM fixes
- embed hw fence in job
- rework dma-resv handling
- ensure eviction to system ram
amdkfd:
- uapi: SVM address range query added
- sysfs leak fix
- GPUVM TLB optimizations
- vmfault/migration counters
i915:
- Enable JSL and EHL by default
- preliminary XeHP/DG2 support
- remove all CNL support (never shipped)
- move to TTM for discrete memory support
- allow mixed object mmap handling
- GEM uAPI spring cleaning
- add I915_MMAP_OBJECT_FIXED
- reinstate ADL-P mmap ioctls
- drop a bunch of unused by userspace features
- disable and remove GPU relocations
- revert some i915 misfeatures
- major refactoring of GuC for Gen11+
- execbuffer object locking separate step
- reject caching/set-domain on discrete
- Enable pipe DMC loading on XE-LPD and ADL-P
- add PSF GV point support
- Refactor and fix DDI buffer translations
- Clean up FBC CFB allocation code
- Finish INTEL_GEN() and friends macro conversions
nouveau:
- add eDP backlight support
- implicit fence fix
msm:
- a680/7c3 support
- drm/scheduler conversion
panfrost:
- rework GPU reset
virtio:
- fix fencing for planes
ast:
- add detect support
bochs:
- move to tiny GPU driver
vc4:
- use hotplug irqs
- HDMI codec support
vmwgfx:
- use internal vmware device headers
ingenic:
- demidlayering irq
rcar-du:
- shutdown fixes
- convert to bridge connector helpers
zynqmp-dsub:
- misc fixes
mgag200:
- convert PLL handling to atomic
mediatek:
- MT8133 AAL support
- gem mmap object support
- MT8167 support
etnaviv:
- NXP Layerscape LS1028A SoC support
- GEM mmap cleanups
tegra:
- new user API
exynos:
- missing unlock fix
- build warning fix
- use refcount_t"
* tag 'drm-next-2021-08-31-1' of git://anongit.freedesktop.org/drm/drm: (1318 commits)
drm/amd/display: Move AllowDRAMSelfRefreshOrDRAMClockChangeInVblank to bounding box
drm/amd/display: Remove duplicate dml init
drm/amd/display: Update bounding box states (v2)
drm/amd/display: Update number of DCN3 clock states
drm/amdgpu: disable GFX CGCG in aldebaran
drm/amdgpu: Clear RAS interrupt status on aldebaran
drm/amdgpu: Add support for RAS XGMI err query
drm/amdkfd: Account for SH/SE count when setting up cu masks.
drm/amdgpu: rename amdgpu_bo_get_preferred_pin_domain
drm/amdgpu: drop redundant cancel_delayed_work_sync call
drm/amdgpu: add missing cleanups for more ASICs on UVD/VCE suspend
drm/amdgpu: add missing cleanups for Polaris12 UVD/VCE on suspend
drm/amdkfd: map SVM range with correct access permission
drm/amdkfd: check access permisson to restore retry fault
drm/amdgpu: Update RAS XGMI Error Query
drm/amdgpu: Add driver infrastructure for MCA RAS
drm/amd/display: Add Logging for HDMI color depth information
drm/amd/amdgpu: consolidate PSP TA init shared buf functions
drm/amd/amdgpu: add name field back to ras_common_if
drm/amdgpu: Fix build with missing pm_suspend_target_state module export
...
This commit is contained in:
Linus Torvalds
@@ -46,7 +46,6 @@
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#include <linux/pci.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_irq.h>
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#include <drm/drm_vblank.h>
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#include <drm/amdgpu_drm.h>
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#include <drm/drm_drv.h>
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@@ -184,7 +183,7 @@ void amdgpu_irq_disable_all(struct amdgpu_device *adev)
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* Returns:
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* result of handling the IRQ, as defined by &irqreturn_t
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*/
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irqreturn_t amdgpu_irq_handler(int irq, void *arg)
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static irqreturn_t amdgpu_irq_handler(int irq, void *arg)
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{
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struct drm_device *dev = (struct drm_device *) arg;
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struct amdgpu_device *adev = drm_to_adev(dev);
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@@ -307,6 +306,7 @@ static void amdgpu_restore_msix(struct amdgpu_device *adev)
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int amdgpu_irq_init(struct amdgpu_device *adev)
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{
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int r = 0;
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unsigned int irq;
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spin_lock_init(&adev->irq.lock);
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@@ -349,15 +349,22 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
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INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2);
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INIT_WORK(&adev->irq.ih_soft_work, amdgpu_irq_handle_ih_soft);
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adev->irq.installed = true;
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/* Use vector 0 for MSI-X */
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r = drm_irq_install(adev_to_drm(adev), pci_irq_vector(adev->pdev, 0));
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/* Use vector 0 for MSI-X. */
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r = pci_irq_vector(adev->pdev, 0);
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if (r < 0)
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return r;
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irq = r;
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/* PCI devices require shared interrupts. */
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r = request_irq(irq, amdgpu_irq_handler, IRQF_SHARED, adev_to_drm(adev)->driver->name,
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adev_to_drm(adev));
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if (r) {
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adev->irq.installed = false;
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if (!amdgpu_device_has_dc_support(adev))
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flush_work(&adev->hotplug_work);
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return r;
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}
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adev->irq.installed = true;
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adev->irq.irq = irq;
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adev_to_drm(adev)->max_vblank_count = 0x00ffffff;
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DRM_DEBUG("amdgpu: irq initialized.\n");
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@@ -368,7 +375,7 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
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void amdgpu_irq_fini_hw(struct amdgpu_device *adev)
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{
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if (adev->irq.installed) {
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drm_irq_uninstall(&adev->ddev);
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free_irq(adev->irq.irq, adev_to_drm(adev));
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adev->irq.installed = false;
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if (adev->irq.msi_enabled)
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pci_free_irq_vectors(adev->pdev);
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@@ -584,7 +591,7 @@ void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
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{
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int i, j, k;
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if (amdgpu_sriov_vf(adev))
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if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
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amdgpu_restore_msix(adev);
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for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
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@@ -617,7 +624,7 @@ void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
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int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
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unsigned type)
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{
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if (!adev_to_drm(adev)->irq_enabled)
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if (!adev->irq.installed)
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return -ENOENT;
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if (type >= src->num_types)
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@@ -647,7 +654,7 @@ int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
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int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
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unsigned type)
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{
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if (!adev_to_drm(adev)->irq_enabled)
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if (!adev->irq.installed)
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return -ENOENT;
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if (type >= src->num_types)
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@@ -678,7 +685,7 @@ int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
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bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
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unsigned type)
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{
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if (!adev_to_drm(adev)->irq_enabled)
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if (!adev->irq.installed)
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return false;
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if (type >= src->num_types)
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