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mlx5: Implement SyncE support using DPLL infrastructure

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Implement SyncE support using newly introduced DPLL support.
Make sure that each PFs/VFs/SFs probed with appropriate capability
will spawn a dpll auxiliary device and register appropriate dpll device
and pin instances.

Signed-off-by: Jiri Pirko <jiri@nvidia.com>
Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Signed-off-by: Vadim Fedorenko <vadim.fedorenko@linux.dev>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jiri Pirko
2023-09-13 21:49:43 +01:00
committed by David S. Miller
parent 09eeb3aecc
commit 496fd0a26b
6 changed files with 520 additions and 1 deletions
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2
include/linux/mlx5/driver.h
View File

@@ -155,6 +155,8 @@ enum {
MLX5_REG_MCC = 0x9062,
MLX5_REG_MCDA = 0x9063,
MLX5_REG_MCAM = 0x907f,
MLX5_REG_MSECQ = 0x9155,
MLX5_REG_MSEES = 0x9156,
MLX5_REG_MIRC = 0x9162,
MLX5_REG_SBCAM = 0xB01F,
MLX5_REG_RESOURCE_DUMP = 0xC000,

59
include/linux/mlx5/mlx5_ifc.h
View File

@@ -10176,7 +10176,9 @@ struct mlx5_ifc_mcam_access_reg_bits2 {
u8 mirc[0x1];
u8 regs_97_to_96[0x2];
u8 regs_95_to_64[0x20];
u8 regs_95_to_87[0x09];
u8 synce_registers[0x2];
u8 regs_84_to_64[0x15];
u8 regs_63_to_32[0x20];
@@ -12549,4 +12551,59 @@ struct mlx5_ifc_modify_page_track_obj_in_bits {
struct mlx5_ifc_page_track_bits obj_context;
};
struct mlx5_ifc_msecq_reg_bits {
u8 reserved_at_0[0x20];
u8 reserved_at_20[0x12];
u8 network_option[0x2];
u8 local_ssm_code[0x4];
u8 local_enhanced_ssm_code[0x8];
u8 local_clock_identity[0x40];
u8 reserved_at_80[0x180];
};
enum {
MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0),
MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1),
MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2),
};
enum mlx5_msees_admin_status {
MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0,
MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1,
};
enum mlx5_msees_oper_status {
MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0,
MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1,
MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2,
MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3,
MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4,
MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5,
};
struct mlx5_ifc_msees_reg_bits {
u8 reserved_at_0[0x8];
u8 local_port[0x8];
u8 pnat[0x2];
u8 lp_msb[0x2];
u8 reserved_at_14[0xc];
u8 field_select[0x20];
u8 admin_status[0x4];
u8 oper_status[0x4];
u8 ho_acq[0x1];
u8 reserved_at_49[0xc];
u8 admin_freq_measure[0x1];
u8 oper_freq_measure[0x1];
u8 failure_reason[0x9];
u8 frequency_diff[0x20];
u8 reserved_at_80[0x180];
};
#endif /* MLX5_IFC_H */