drm/i915: Workaround erratum on i830 for TAIL pointer within last 2 cachelines

On i830 if the tail pointer is set to within 2 cachelines of the end of
the buffer, the chip may hang. So instead if the tail were to land in
that location, we pad the end of the buffer with NOPs, and start again
at the beginning.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

drivers/gpu/drm/i915/intel_ringbuffer.h

@@ -49,6 +49,7 @@ struct  intel_ring_buffer {
 	u32		tail;
 	int		space;
 	int		size;
+	int		effective_size;
 	struct intel_hw_status_page status_page;
 
 	u32		irq_seqno;		/* last seq seem at irq time */