mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
synced 2026-04-20 04:23:55 -04:00
Merge tag 'amd-drm-next-5.14-2021-06-02' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-5.14-2021-06-02:
amdgpu:
- GC/MM register access macro clean up for SR-IOV
- Beige Goby updates
- W=1 Fixes
- Aldebaran fixes
- Misc display fixes
- ACPI ATCS/ATIF handling rework
- SR-IOV fixes
- RAS fixes
- 16bpc fixed point format support
- Initial smartshift support
- RV/PCO power tuning fixes for suspend/resume
- More buffer object subclassing work
- Add new INFO query for additional vbios information
- Add new placement for preemptable SG buffers
amdkfd:
- Misc fixes
radeon:
- W=1 Fixes
- Misc cleanups
UAPI:
- Add new INFO query for additional vbios information
Useful for debugging vbios related issues. Proposed umr patch:
https://patchwork.freedesktop.org/patch/433297/
- 16bpc fixed point format support
IGT test:
https://lists.freedesktop.org/archives/igt-dev/2021-May/031507.html
Proposed Vulkan patch:
a25d480207
- Add a new GEM flag which is only used internally in the kernel driver. Userspace
is not allowed to set it.
drm:
- 16bpc fixed point format fourcc
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210602214009.4553-1-alexander.deucher@amd.com
This commit is contained in:
Dave Airlie
@@ -30,7 +30,7 @@ struct IP_BASE_INSTANCE {
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struct IP_BASE {
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struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
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};
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} __maybe_unused;
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static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C20, 0x02408C00, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0, 0 } },
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@@ -103,6 +103,13 @@ struct atcs_pref_req_output {
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u8 ret_val; /* return value */
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} __packed;
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struct atcs_pwr_shift_input {
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u16 size; /* structure size in bytes (includes size field) */
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u16 dgpu_id; /* client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */
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u8 dev_acpi_state; /* D0 = 0, D3 hot = 3 */
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u8 drv_state; /* 0 = operational, 1 = not operational */
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} __packed;
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/* AMD hw uses four ACPI control methods:
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* 1. ATIF
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* ARG0: (ACPI_INTEGER) function code
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@@ -418,6 +425,7 @@ struct atcs_pref_req_output {
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# define ATCS_PCIE_PERFORMANCE_REQUEST_SUPPORTED (1 << 1)
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# define ATCS_PCIE_DEVICE_READY_NOTIFICATION_SUPPORTED (1 << 2)
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# define ATCS_SET_PCIE_BUS_WIDTH_SUPPORTED (1 << 3)
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# define ATCS_SET_POWER_SHIFT_CONTROL_SUPPORTED (1 << 7)
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#define ATCS_FUNCTION_GET_EXTERNAL_STATE 0x1
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/* ARG0: ATCS_FUNCTION_GET_EXTERNAL_STATE
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* ARG1: none
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@@ -472,4 +480,14 @@ struct atcs_pref_req_output {
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* BYTE - number of active lanes
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*/
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#define ATCS_FUNCTION_POWER_SHIFT_CONTROL 0x8
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/* ARG0: ATCS_FUNCTION_POWER_SHIFT_CONTROL
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* ARG1:
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* WORD - structure size in bytes (includes size field)
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* WORD - dGPU id (bit 2-0: func num, 7-3: dev num, 15-8: bus num)
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* BYTE - Device ACPI state
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* BYTE - Driver state
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* OUTPUT: none
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*/
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#endif
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@@ -197,6 +197,9 @@ enum atom_dp_vs_preemph_def{
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DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18,
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};
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#define BIOS_ATOM_PREFIX "ATOMBIOS"
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#define BIOS_VERSION_PREFIX "ATOMBIOSBK-AMD"
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#define BIOS_STRING_LENGTH 43
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/*
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enum atom_string_def{
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@@ -209,12 +212,14 @@ atom_bios_string = "ATOM"
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#pragma pack(1) /* BIOS data must use byte aligment*/
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enum atombios_image_offset{
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OFFSET_TO_ATOM_ROM_HEADER_POINTER =0x00000048,
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OFFSET_TO_ATOM_ROM_IMAGE_SIZE =0x00000002,
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OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE =0x94,
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MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE =20, /*including the terminator 0x0!*/
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OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS =0x2f,
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OFFSET_TO_GET_ATOMBIOS_STRING_START =0x6e,
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OFFSET_TO_ATOM_ROM_HEADER_POINTER = 0x00000048,
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OFFSET_TO_ATOM_ROM_IMAGE_SIZE = 0x00000002,
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OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE = 0x94,
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MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE = 20, /*including the terminator 0x0!*/
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OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS = 0x2f,
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OFFSET_TO_GET_ATOMBIOS_STRING_START = 0x6e,
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OFFSET_TO_VBIOS_PART_NUMBER = 0x80,
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OFFSET_TO_VBIOS_DATE = 0x50,
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};
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/****************************************************************************
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@@ -536,6 +536,75 @@ struct gpu_metrics_v1_2 {
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uint64_t firmware_timestamp;
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};
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struct gpu_metrics_v1_3 {
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struct metrics_table_header common_header;
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/* Temperature */
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uint16_t temperature_edge;
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uint16_t temperature_hotspot;
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uint16_t temperature_mem;
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uint16_t temperature_vrgfx;
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uint16_t temperature_vrsoc;
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uint16_t temperature_vrmem;
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/* Utilization */
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uint16_t average_gfx_activity;
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uint16_t average_umc_activity; // memory controller
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uint16_t average_mm_activity; // UVD or VCN
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/* Power/Energy */
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uint16_t average_socket_power;
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uint64_t energy_accumulator;
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/* Driver attached timestamp (in ns) */
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uint64_t system_clock_counter;
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/* Average clocks */
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uint16_t average_gfxclk_frequency;
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uint16_t average_socclk_frequency;
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uint16_t average_uclk_frequency;
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uint16_t average_vclk0_frequency;
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uint16_t average_dclk0_frequency;
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uint16_t average_vclk1_frequency;
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uint16_t average_dclk1_frequency;
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/* Current clocks */
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uint16_t current_gfxclk;
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uint16_t current_socclk;
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uint16_t current_uclk;
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uint16_t current_vclk0;
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uint16_t current_dclk0;
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uint16_t current_vclk1;
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uint16_t current_dclk1;
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/* Throttle status */
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uint32_t throttle_status;
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/* Fans */
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uint16_t current_fan_speed;
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/* Link width/speed */
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uint16_t pcie_link_width;
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uint16_t pcie_link_speed; // in 0.1 GT/s
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uint16_t padding;
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uint32_t gfx_activity_acc;
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uint32_t mem_activity_acc;
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uint16_t temperature_hbm[NUM_HBM_INSTANCES];
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/* PMFW attached timestamp (10ns resolution) */
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uint64_t firmware_timestamp;
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/* Voltage (mV) */
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uint16_t voltage_soc;
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uint16_t voltage_gfx;
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uint16_t voltage_mem;
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uint16_t padding1;
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};
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/*
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* gpu_metrics_v2_0 is not recommended as it's not naturally aligned.
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* Use gpu_metrics_v2_1 or later instead.
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