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dt-bindings: riscv: Sort the CPU core list alphabetically

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Sort the CPU cores list alphabetically for maintenance.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20221028165921.94487-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar
2022-10-28 17:59:15 +01:00
committed by Geert Uytterhoeven
parent 7dd1d57c05
commit 57e1b873c2
1 changed files with 5 additions and 5 deletions
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10
Documentation/devicetree/bindings/riscv/cpus.yaml
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@@ -28,17 +28,17 @@ properties:
oneOf:
- items:
- enum:
- sifive,rocket0
- canaan,k210
- sifive,bullet0
- sifive,e5
- sifive,e7
- sifive,e71
- sifive,u74-mc
- sifive,u54
- sifive,u74
- sifive,rocket0
- sifive,u5
- sifive,u54
- sifive,u7
- canaan,k210
- sifive,u74
- sifive,u74-mc
- const: riscv
- items:
- enum: