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liquidio: Simplified napi poll

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1) Moved interrupt enable related code from octeon_process_droq_poll_cmd()
   to separate function octeon_enable_irq().
2) Removed wrapper function octeon_process_droq_poll_cmd(), and directlyi
   using octeon_droq_process_poll_pkts().
3) Removed unused macros POLL_EVENT_XXX.

Signed-off-by: Intiyaz Basha <intiyaz.basha@cavium.com>
Signed-off-by: Felix Manlunas <felix.manlunas@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Intiyaz Basha
2018-03-16 10:21:31 -07:00
committed by David S. Miller
parent b8124b53d1
commit 5eb297a9a5
3 changed files with 35 additions and 66 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/net/ethernet/cavium/liquidio/lio_core.c
View File

@@ -627,9 +627,7 @@ static int liquidio_napi_poll(struct napi_struct *napi, int budget)
iq_no = droq->q_no; iq_no = droq->q_no;
/* Handle Droq descriptors */ /* Handle Droq descriptors */
work_done = octeon_process_droq_poll_cmd(oct, droq->q_no, work_done = octeon_droq_process_poll_pkts(oct, droq, budget);
POLL_EVENT_PROCESS_PKTS,
budget);
/* Flush the instruction queue */ /* Flush the instruction queue */
iq = oct->instr_queue[iq_no]; iq = oct->instr_queue[iq_no];
@@ -660,8 +658,7 @@ static int liquidio_napi_poll(struct napi_struct *napi, int budget)
tx_done = 1; tx_done = 1;
napi_complete_done(napi, work_done); napi_complete_done(napi, work_done);
octeon_process_droq_poll_cmd(droq->oct_dev, droq->q_no, octeon_enable_irq(droq->oct_dev, droq->q_no);
POLL_EVENT_ENABLE_INTR, 0);
return 0; return 0;
} }

83
drivers/net/ethernet/cavium/liquidio/octeon_droq.c
View File

@@ -788,7 +788,7 @@ octeon_droq_process_packets(struct octeon_device *oct,
* called before calling this routine. * called before calling this routine.
*/ */
static int int
octeon_droq_process_poll_pkts(struct octeon_device *oct, octeon_droq_process_poll_pkts(struct octeon_device *oct,
struct octeon_droq *droq, u32 budget) struct octeon_droq *droq, u32 budget)
{ {
@@ -835,71 +835,46 @@ octeon_droq_process_poll_pkts(struct octeon_device *oct,
return total_pkts_processed; return total_pkts_processed;
} }
/* Enable Pkt Interrupt */
int int
octeon_process_droq_poll_cmd(struct octeon_device *oct, u32 q_no, int cmd, octeon_enable_irq(struct octeon_device *oct, u32 q_no)
u32 arg)
{ {
struct octeon_droq *droq; switch (oct->chip_id) {
case OCTEON_CN66XX:
droq = oct->droq[q_no]; case OCTEON_CN68XX: {
struct octeon_cn6xxx *cn6xxx =
if (cmd == POLL_EVENT_PROCESS_PKTS) (struct octeon_cn6xxx *)oct->chip;
return octeon_droq_process_poll_pkts(oct, droq, arg);
if (cmd == POLL_EVENT_PENDING_PKTS) {
u32 pkt_cnt = atomic_read(&droq->pkts_pending);
return octeon_droq_process_packets(oct, droq, pkt_cnt);
}
if (cmd == POLL_EVENT_ENABLE_INTR) {
u32 value;
unsigned long flags; unsigned long flags;
u32 value;
/* Enable Pkt Interrupt */ spin_lock_irqsave
switch (oct->chip_id) { (&cn6xxx->lock_for_droq_int_enb_reg, flags);
case OCTEON_CN66XX: value = octeon_read_csr(oct, CN6XXX_SLI_PKT_TIME_INT_ENB);
case OCTEON_CN68XX: { value |= (1 << q_no);
struct octeon_cn6xxx *cn6xxx = octeon_write_csr(oct, CN6XXX_SLI_PKT_TIME_INT_ENB, value);
(struct octeon_cn6xxx *)oct->chip; value = octeon_read_csr(oct, CN6XXX_SLI_PKT_CNT_INT_ENB);
spin_lock_irqsave value |= (1 << q_no);
(&cn6xxx->lock_for_droq_int_enb_reg, flags); octeon_write_csr(oct, CN6XXX_SLI_PKT_CNT_INT_ENB, value);
value =
octeon_read_csr(oct,
CN6XXX_SLI_PKT_TIME_INT_ENB);
value |= (1 << q_no);
octeon_write_csr(oct,
CN6XXX_SLI_PKT_TIME_INT_ENB,
value);
value =
octeon_read_csr(oct,
CN6XXX_SLI_PKT_CNT_INT_ENB);
value |= (1 << q_no);
octeon_write_csr(oct,
CN6XXX_SLI_PKT_CNT_INT_ENB,
value);
/* don't bother flushing the enables */ /* don't bother flushing the enables */
spin_unlock_irqrestore spin_unlock_irqrestore
(&cn6xxx->lock_for_droq_int_enb_reg, flags); (&cn6xxx->lock_for_droq_int_enb_reg, flags);
return 0; }
}
break; break;
case OCTEON_CN23XX_PF_VID: { case OCTEON_CN23XX_PF_VID:
lio_enable_irq(oct->droq[q_no], oct->instr_queue[q_no]); lio_enable_irq(oct->droq[q_no], oct->instr_queue[q_no]);
}
break; break;
case OCTEON_CN23XX_VF_VID: case OCTEON_CN23XX_VF_VID:
lio_enable_irq(oct->droq[q_no], oct->instr_queue[q_no]); lio_enable_irq(oct->droq[q_no], oct->instr_queue[q_no]);
break; break;
} default:
return 0; dev_err(&oct->pci_dev->dev, "%s Unknown Chip\n", __func__);
return 1;
} }
dev_err(&oct->pci_dev->dev, "%s Unknown command: %d\n", __func__, cmd); return 0;
return -EINVAL;
} }
int octeon_register_droq_ops(struct octeon_device *oct, u32 q_no, int octeon_register_droq_ops(struct octeon_device *oct, u32 q_no,

11
drivers/net/ethernet/cavium/liquidio/octeon_droq.h
View File

@@ -123,11 +123,6 @@ struct oct_droq_stats {
}; };
#define POLL_EVENT_INTR_ARRIVED 1
#define POLL_EVENT_PROCESS_PKTS 2
#define POLL_EVENT_PENDING_PKTS 3
#define POLL_EVENT_ENABLE_INTR 4
/* The maximum number of buffers that can be dispatched from the /* The maximum number of buffers that can be dispatched from the
* output/dma queue. Set to 64 assuming 1K buffers in DROQ and the fact that * output/dma queue. Set to 64 assuming 1K buffers in DROQ and the fact that
* max packet size from DROQ is 64K. * max packet size from DROQ is 64K.
@@ -414,8 +409,10 @@ int octeon_droq_process_packets(struct octeon_device *oct,
struct octeon_droq *droq, struct octeon_droq *droq,
u32 budget); u32 budget);
int octeon_process_droq_poll_cmd(struct octeon_device *oct, u32 q_no, int octeon_droq_process_poll_pkts(struct octeon_device *oct,
int cmd, u32 arg); struct octeon_droq *droq, u32 budget);
int octeon_enable_irq(struct octeon_device *oct, u32 q_no);
void octeon_droq_check_oom(struct octeon_droq *droq); void octeon_droq_check_oom(struct octeon_droq *droq);