mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
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drm/amdgpu: separate VMID and PASID handling
Move both into the new files amdgpu_ids.[ch]. No functional change. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Christian König
committed by
Alex Deucher
Alex Deucher
parent
df2869abd9
commit
620f774f46
@@ -33,52 +33,6 @@
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#include "amdgpu.h"
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#include "amdgpu_trace.h"
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/*
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* PASID manager
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*
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* PASIDs are global address space identifiers that can be shared
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* between the GPU, an IOMMU and the driver. VMs on different devices
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* may use the same PASID if they share the same address
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* space. Therefore PASIDs are allocated using a global IDA. VMs are
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* looked up from the PASID per amdgpu_device.
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*/
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static DEFINE_IDA(amdgpu_vm_pasid_ida);
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/**
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* amdgpu_vm_alloc_pasid - Allocate a PASID
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* @bits: Maximum width of the PASID in bits, must be at least 1
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*
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* Allocates a PASID of the given width while keeping smaller PASIDs
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* available if possible.
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*
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* Returns a positive integer on success. Returns %-EINVAL if bits==0.
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* Returns %-ENOSPC if no PASID was available. Returns %-ENOMEM on
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* memory allocation failure.
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*/
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int amdgpu_vm_alloc_pasid(unsigned int bits)
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{
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int pasid = -EINVAL;
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for (bits = min(bits, 31U); bits > 0; bits--) {
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pasid = ida_simple_get(&amdgpu_vm_pasid_ida,
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1U << (bits - 1), 1U << bits,
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GFP_KERNEL);
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if (pasid != -ENOSPC)
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break;
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}
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return pasid;
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}
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/**
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* amdgpu_vm_free_pasid - Free a PASID
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* @pasid: PASID to free
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*/
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void amdgpu_vm_free_pasid(unsigned int pasid)
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{
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ida_simple_remove(&amdgpu_vm_pasid_ida, pasid);
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}
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/*
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* GPUVM
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* GPUVM is similar to the legacy gart on older asics, however
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@@ -447,286 +401,6 @@ int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
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adev->vm_manager.root_level);
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}
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/**
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* amdgpu_vm_had_gpu_reset - check if reset occured since last use
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*
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* @adev: amdgpu_device pointer
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* @id: VMID structure
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*
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* Check if GPU reset occured since last use of the VMID.
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*/
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static bool amdgpu_vm_had_gpu_reset(struct amdgpu_device *adev,
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struct amdgpu_vm_id *id)
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{
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return id->current_gpu_reset_count !=
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atomic_read(&adev->gpu_reset_counter);
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}
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static bool amdgpu_vm_reserved_vmid_ready(struct amdgpu_vm *vm, unsigned vmhub)
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{
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return !!vm->reserved_vmid[vmhub];
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}
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/* idr_mgr->lock must be held */
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static int amdgpu_vm_grab_reserved_vmid_locked(struct amdgpu_vm *vm,
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struct amdgpu_ring *ring,
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struct amdgpu_sync *sync,
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struct dma_fence *fence,
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struct amdgpu_job *job)
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{
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struct amdgpu_device *adev = ring->adev;
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unsigned vmhub = ring->funcs->vmhub;
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uint64_t fence_context = adev->fence_context + ring->idx;
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struct amdgpu_vm_id *id = vm->reserved_vmid[vmhub];
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struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
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struct dma_fence *updates = sync->last_vm_update;
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int r = 0;
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struct dma_fence *flushed, *tmp;
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bool needs_flush = vm->use_cpu_for_update;
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flushed = id->flushed_updates;
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if ((amdgpu_vm_had_gpu_reset(adev, id)) ||
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(atomic64_read(&id->owner) != vm->client_id) ||
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(job->vm_pd_addr != id->pd_gpu_addr) ||
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(updates && (!flushed || updates->context != flushed->context ||
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dma_fence_is_later(updates, flushed))) ||
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(!id->last_flush || (id->last_flush->context != fence_context &&
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!dma_fence_is_signaled(id->last_flush)))) {
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needs_flush = true;
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/* to prevent one context starved by another context */
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id->pd_gpu_addr = 0;
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tmp = amdgpu_sync_peek_fence(&id->active, ring);
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if (tmp) {
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r = amdgpu_sync_fence(adev, sync, tmp, false);
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return r;
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}
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}
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/* Good we can use this VMID. Remember this submission as
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* user of the VMID.
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*/
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r = amdgpu_sync_fence(ring->adev, &id->active, fence, false);
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if (r)
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goto out;
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if (updates && (!flushed || updates->context != flushed->context ||
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dma_fence_is_later(updates, flushed))) {
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dma_fence_put(id->flushed_updates);
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id->flushed_updates = dma_fence_get(updates);
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}
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id->pd_gpu_addr = job->vm_pd_addr;
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atomic64_set(&id->owner, vm->client_id);
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job->vm_needs_flush = needs_flush;
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if (needs_flush) {
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dma_fence_put(id->last_flush);
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id->last_flush = NULL;
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}
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job->vm_id = id - id_mgr->ids;
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trace_amdgpu_vm_grab_id(vm, ring, job);
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out:
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return r;
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}
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/**
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* amdgpu_vm_grab_id - allocate the next free VMID
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*
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* @vm: vm to allocate id for
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* @ring: ring we want to submit job to
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* @sync: sync object where we add dependencies
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* @fence: fence protecting ID from reuse
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*
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* Allocate an id for the vm, adding fences to the sync obj as necessary.
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*/
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int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
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struct amdgpu_sync *sync, struct dma_fence *fence,
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struct amdgpu_job *job)
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{
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struct amdgpu_device *adev = ring->adev;
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unsigned vmhub = ring->funcs->vmhub;
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struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
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uint64_t fence_context = adev->fence_context + ring->idx;
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struct dma_fence *updates = sync->last_vm_update;
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struct amdgpu_vm_id *id, *idle;
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struct dma_fence **fences;
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unsigned i;
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int r = 0;
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mutex_lock(&id_mgr->lock);
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if (amdgpu_vm_reserved_vmid_ready(vm, vmhub)) {
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r = amdgpu_vm_grab_reserved_vmid_locked(vm, ring, sync, fence, job);
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mutex_unlock(&id_mgr->lock);
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return r;
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}
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fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_KERNEL);
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if (!fences) {
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mutex_unlock(&id_mgr->lock);
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return -ENOMEM;
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}
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/* Check if we have an idle VMID */
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i = 0;
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list_for_each_entry(idle, &id_mgr->ids_lru, list) {
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fences[i] = amdgpu_sync_peek_fence(&idle->active, ring);
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if (!fences[i])
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break;
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++i;
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}
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/* If we can't find a idle VMID to use, wait till one becomes available */
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if (&idle->list == &id_mgr->ids_lru) {
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u64 fence_context = adev->vm_manager.fence_context + ring->idx;
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unsigned seqno = ++adev->vm_manager.seqno[ring->idx];
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struct dma_fence_array *array;
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unsigned j;
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for (j = 0; j < i; ++j)
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dma_fence_get(fences[j]);
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array = dma_fence_array_create(i, fences, fence_context,
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seqno, true);
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if (!array) {
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for (j = 0; j < i; ++j)
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dma_fence_put(fences[j]);
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kfree(fences);
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r = -ENOMEM;
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goto error;
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}
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r = amdgpu_sync_fence(ring->adev, sync, &array->base, false);
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dma_fence_put(&array->base);
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if (r)
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goto error;
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mutex_unlock(&id_mgr->lock);
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return 0;
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}
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kfree(fences);
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job->vm_needs_flush = vm->use_cpu_for_update;
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/* Check if we can use a VMID already assigned to this VM */
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list_for_each_entry_reverse(id, &id_mgr->ids_lru, list) {
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struct dma_fence *flushed;
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bool needs_flush = vm->use_cpu_for_update;
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/* Check all the prerequisites to using this VMID */
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if (amdgpu_vm_had_gpu_reset(adev, id))
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continue;
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if (atomic64_read(&id->owner) != vm->client_id)
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continue;
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if (job->vm_pd_addr != id->pd_gpu_addr)
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continue;
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if (!id->last_flush ||
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(id->last_flush->context != fence_context &&
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!dma_fence_is_signaled(id->last_flush)))
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needs_flush = true;
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flushed = id->flushed_updates;
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if (updates && (!flushed || dma_fence_is_later(updates, flushed)))
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needs_flush = true;
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/* Concurrent flushes are only possible starting with Vega10 */
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if (adev->asic_type < CHIP_VEGA10 && needs_flush)
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continue;
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/* Good we can use this VMID. Remember this submission as
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* user of the VMID.
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*/
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r = amdgpu_sync_fence(ring->adev, &id->active, fence, false);
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if (r)
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goto error;
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if (updates && (!flushed || dma_fence_is_later(updates, flushed))) {
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dma_fence_put(id->flushed_updates);
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id->flushed_updates = dma_fence_get(updates);
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}
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if (needs_flush)
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goto needs_flush;
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else
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goto no_flush_needed;
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};
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/* Still no ID to use? Then use the idle one found earlier */
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id = idle;
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/* Remember this submission as user of the VMID */
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r = amdgpu_sync_fence(ring->adev, &id->active, fence, false);
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if (r)
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goto error;
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id->pd_gpu_addr = job->vm_pd_addr;
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dma_fence_put(id->flushed_updates);
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id->flushed_updates = dma_fence_get(updates);
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atomic64_set(&id->owner, vm->client_id);
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needs_flush:
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job->vm_needs_flush = true;
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dma_fence_put(id->last_flush);
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id->last_flush = NULL;
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no_flush_needed:
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list_move_tail(&id->list, &id_mgr->ids_lru);
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job->vm_id = id - id_mgr->ids;
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trace_amdgpu_vm_grab_id(vm, ring, job);
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error:
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mutex_unlock(&id_mgr->lock);
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return r;
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}
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static void amdgpu_vm_free_reserved_vmid(struct amdgpu_device *adev,
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struct amdgpu_vm *vm,
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unsigned vmhub)
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{
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struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
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mutex_lock(&id_mgr->lock);
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if (vm->reserved_vmid[vmhub]) {
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list_add(&vm->reserved_vmid[vmhub]->list,
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&id_mgr->ids_lru);
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vm->reserved_vmid[vmhub] = NULL;
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atomic_dec(&id_mgr->reserved_vmid_num);
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}
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mutex_unlock(&id_mgr->lock);
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}
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static int amdgpu_vm_alloc_reserved_vmid(struct amdgpu_device *adev,
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struct amdgpu_vm *vm,
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unsigned vmhub)
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{
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struct amdgpu_vm_id_manager *id_mgr;
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struct amdgpu_vm_id *idle;
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int r = 0;
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id_mgr = &adev->vm_manager.id_mgr[vmhub];
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mutex_lock(&id_mgr->lock);
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if (vm->reserved_vmid[vmhub])
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goto unlock;
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if (atomic_inc_return(&id_mgr->reserved_vmid_num) >
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AMDGPU_VM_MAX_RESERVED_VMID) {
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DRM_ERROR("Over limitation of reserved vmid\n");
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atomic_dec(&id_mgr->reserved_vmid_num);
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r = -EINVAL;
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goto unlock;
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}
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/* Select the first entry VMID */
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idle = list_first_entry(&id_mgr->ids_lru, struct amdgpu_vm_id, list);
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list_del_init(&idle->list);
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vm->reserved_vmid[vmhub] = idle;
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mutex_unlock(&id_mgr->lock);
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return 0;
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unlock:
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mutex_unlock(&id_mgr->lock);
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return r;
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}
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/**
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* amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
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*
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@@ -767,8 +441,8 @@ bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
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{
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struct amdgpu_device *adev = ring->adev;
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unsigned vmhub = ring->funcs->vmhub;
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struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
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struct amdgpu_vm_id *id;
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struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
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struct amdgpu_vmid *id;
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bool gds_switch_needed;
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bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
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@@ -783,7 +457,7 @@ bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
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id->oa_base != job->oa_base ||
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id->oa_size != job->oa_size);
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if (amdgpu_vm_had_gpu_reset(adev, id))
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if (amdgpu_vmid_had_gpu_reset(adev, id))
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return true;
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return vm_flush_needed || gds_switch_needed;
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@@ -807,8 +481,8 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_
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{
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struct amdgpu_device *adev = ring->adev;
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unsigned vmhub = ring->funcs->vmhub;
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struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
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struct amdgpu_vm_id *id = &id_mgr->ids[job->vm_id];
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struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
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struct amdgpu_vmid *id = &id_mgr->ids[job->vm_id];
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bool gds_switch_needed = ring->funcs->emit_gds_switch && (
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id->gds_base != job->gds_base ||
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id->gds_size != job->gds_size ||
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@@ -820,7 +494,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_
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unsigned patch_offset = 0;
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int r;
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if (amdgpu_vm_had_gpu_reset(adev, id)) {
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if (amdgpu_vmid_had_gpu_reset(adev, id)) {
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gds_switch_needed = true;
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vm_flush_needed = true;
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}
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@@ -875,49 +549,6 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_
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return 0;
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}
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/**
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* amdgpu_vm_reset_id - reset VMID to zero
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*
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* @adev: amdgpu device structure
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* @vm_id: vmid number to use
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*
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* Reset saved GDW, GWS and OA to force switch on next flush.
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*/
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void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub,
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unsigned vmid)
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{
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struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
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struct amdgpu_vm_id *id = &id_mgr->ids[vmid];
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atomic64_set(&id->owner, 0);
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id->gds_base = 0;
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id->gds_size = 0;
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id->gws_base = 0;
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id->gws_size = 0;
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id->oa_base = 0;
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id->oa_size = 0;
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}
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/**
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* amdgpu_vm_reset_all_id - reset VMID to zero
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*
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* @adev: amdgpu device structure
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*
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* Reset VMID to force flush on next use
|
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*/
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void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev)
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{
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unsigned i, j;
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|
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for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
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struct amdgpu_vm_id_manager *id_mgr =
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&adev->vm_manager.id_mgr[i];
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for (j = 1; j < id_mgr->num_ids; ++j)
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amdgpu_vm_reset_id(adev, i, j);
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}
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}
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/**
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* amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
|
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*
|
||||
@@ -2819,7 +2450,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
|
||||
amdgpu_bo_unref(&root);
|
||||
dma_fence_put(vm->last_update);
|
||||
for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
|
||||
amdgpu_vm_free_reserved_vmid(adev, vm, i);
|
||||
amdgpu_vmid_free_reserved(adev, vm, i);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -2861,23 +2492,9 @@ bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev,
|
||||
*/
|
||||
void amdgpu_vm_manager_init(struct amdgpu_device *adev)
|
||||
{
|
||||
unsigned i, j;
|
||||
unsigned i;
|
||||
|
||||
for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
|
||||
struct amdgpu_vm_id_manager *id_mgr =
|
||||
&adev->vm_manager.id_mgr[i];
|
||||
|
||||
mutex_init(&id_mgr->lock);
|
||||
INIT_LIST_HEAD(&id_mgr->ids_lru);
|
||||
atomic_set(&id_mgr->reserved_vmid_num, 0);
|
||||
|
||||
/* skip over VMID 0, since it is the system VM */
|
||||
for (j = 1; j < id_mgr->num_ids; ++j) {
|
||||
amdgpu_vm_reset_id(adev, i, j);
|
||||
amdgpu_sync_create(&id_mgr->ids[i].active);
|
||||
list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru);
|
||||
}
|
||||
}
|
||||
amdgpu_vmid_mgr_init(adev);
|
||||
|
||||
adev->vm_manager.fence_context =
|
||||
dma_fence_context_alloc(AMDGPU_MAX_RINGS);
|
||||
@@ -2918,24 +2535,10 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev)
|
||||
*/
|
||||
void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
|
||||
{
|
||||
unsigned i, j;
|
||||
|
||||
WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr));
|
||||
idr_destroy(&adev->vm_manager.pasid_idr);
|
||||
|
||||
for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
|
||||
struct amdgpu_vm_id_manager *id_mgr =
|
||||
&adev->vm_manager.id_mgr[i];
|
||||
|
||||
mutex_destroy(&id_mgr->lock);
|
||||
for (j = 0; j < AMDGPU_NUM_VM; ++j) {
|
||||
struct amdgpu_vm_id *id = &id_mgr->ids[j];
|
||||
|
||||
amdgpu_sync_free(&id->active);
|
||||
dma_fence_put(id->flushed_updates);
|
||||
dma_fence_put(id->last_flush);
|
||||
}
|
||||
}
|
||||
amdgpu_vmid_mgr_fini(adev);
|
||||
}
|
||||
|
||||
int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
|
||||
@@ -2948,13 +2551,12 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
|
||||
switch (args->in.op) {
|
||||
case AMDGPU_VM_OP_RESERVE_VMID:
|
||||
/* current, we only have requirement to reserve vmid from gfxhub */
|
||||
r = amdgpu_vm_alloc_reserved_vmid(adev, &fpriv->vm,
|
||||
AMDGPU_GFXHUB);
|
||||
r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
|
||||
if (r)
|
||||
return r;
|
||||
break;
|
||||
case AMDGPU_VM_OP_UNRESERVE_VMID:
|
||||
amdgpu_vm_free_reserved_vmid(adev, &fpriv->vm, AMDGPU_GFXHUB);
|
||||
amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
|
||||
Reference in New Issue
Block a user