mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
synced 2026-04-23 05:56:14 -04:00
KVM: arm64: selftests: Remove the hard-coded {b,w}pn#0 from debug-exceptions
Remove the hard-coded {break,watch}point #0 from the guest_code() in
debug-exceptions to allow {break,watch}point number to be specified.
Change reset_debug_state() to zeroing all dbg{b,w}{c,v}r_el0 registers
so that guest_code() can use the function to reset those registers
even when non-zero {break,watch}points are specified for guest_code().
Subsequent patches will add test cases for non-zero {break,watch}points.
Signed-off-by: Reiji Watanabe <reijiw@google.com>
Reviewed-by: Ricardo Koller <ricarkol@google.com>
Reviewed-by: Oliver Upton <oliver.upton@linux.dev>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20221020054202.2119018-4-reijiw@google.com
This commit is contained in:
committed by
Marc Zyngier
parent
f6d02aa28a
commit
700b8860e0
@@ -95,6 +95,9 @@ GEN_DEBUG_WRITE_REG(dbgwvr)
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static void reset_debug_state(void)
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{
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uint8_t brps, wrps, i;
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uint64_t dfr0;
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asm volatile("msr daifset, #8");
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write_sysreg(0, osdlr_el1);
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@@ -102,11 +105,20 @@ static void reset_debug_state(void)
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isb();
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write_sysreg(0, mdscr_el1);
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/* This test only uses the first bp and wp slot. */
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write_sysreg(0, dbgbvr0_el1);
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write_sysreg(0, dbgbcr0_el1);
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write_sysreg(0, dbgwcr0_el1);
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write_sysreg(0, dbgwvr0_el1);
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/* Reset all bcr/bvr/wcr/wvr registers */
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dfr0 = read_sysreg(id_aa64dfr0_el1);
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brps = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_BRPS), dfr0);
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for (i = 0; i <= brps; i++) {
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write_dbgbcr(i, 0);
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write_dbgbvr(i, 0);
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}
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wrps = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_WRPS), dfr0);
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for (i = 0; i <= wrps; i++) {
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write_dbgwcr(i, 0);
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write_dbgwvr(i, 0);
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}
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isb();
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}
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@@ -118,14 +130,14 @@ static void enable_os_lock(void)
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GUEST_ASSERT(read_sysreg(oslsr_el1) & 2);
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}
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static void install_wp(uint64_t addr)
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static void install_wp(uint8_t wpn, uint64_t addr)
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{
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uint32_t wcr;
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uint32_t mdscr;
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wcr = DBGWCR_LEN8 | DBGWCR_RD | DBGWCR_WR | DBGWCR_EL1 | DBGWCR_E;
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write_dbgwcr(0, wcr);
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write_dbgwvr(0, addr);
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write_dbgwcr(wpn, wcr);
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write_dbgwvr(wpn, addr);
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isb();
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@@ -136,14 +148,14 @@ static void install_wp(uint64_t addr)
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isb();
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}
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static void install_hw_bp(uint64_t addr)
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static void install_hw_bp(uint8_t bpn, uint64_t addr)
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{
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uint32_t bcr;
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uint32_t mdscr;
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bcr = DBGBCR_LEN8 | DBGBCR_EXEC | DBGBCR_EL1 | DBGBCR_E;
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write_dbgbcr(0, bcr);
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write_dbgbvr(0, addr);
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write_dbgbcr(bpn, bcr);
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write_dbgbvr(bpn, addr);
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isb();
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asm volatile("msr daifclr, #8");
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@@ -166,7 +178,7 @@ static void install_ss(void)
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static volatile char write_data;
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static void guest_code(void)
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static void guest_code(uint8_t bpn, uint8_t wpn)
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{
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GUEST_SYNC(0);
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@@ -179,7 +191,7 @@ static void guest_code(void)
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/* Hardware-breakpoint */
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reset_debug_state();
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install_hw_bp(PC(hw_bp));
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install_hw_bp(bpn, PC(hw_bp));
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asm volatile("hw_bp: nop");
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GUEST_ASSERT_EQ(hw_bp_addr, PC(hw_bp));
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@@ -187,7 +199,7 @@ static void guest_code(void)
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/* Hardware-breakpoint + svc */
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reset_debug_state();
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install_hw_bp(PC(bp_svc));
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install_hw_bp(bpn, PC(bp_svc));
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asm volatile("bp_svc: svc #0");
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GUEST_ASSERT_EQ(hw_bp_addr, PC(bp_svc));
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GUEST_ASSERT_EQ(svc_addr, PC(bp_svc) + 4);
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@@ -196,7 +208,7 @@ static void guest_code(void)
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/* Hardware-breakpoint + software-breakpoint */
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reset_debug_state();
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install_hw_bp(PC(bp_brk));
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install_hw_bp(bpn, PC(bp_brk));
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asm volatile("bp_brk: brk #0");
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GUEST_ASSERT_EQ(sw_bp_addr, PC(bp_brk));
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GUEST_ASSERT_EQ(hw_bp_addr, PC(bp_brk));
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@@ -205,7 +217,7 @@ static void guest_code(void)
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/* Watchpoint */
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reset_debug_state();
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install_wp(PC(write_data));
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install_wp(wpn, PC(write_data));
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write_data = 'x';
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GUEST_ASSERT_EQ(write_data, 'x');
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GUEST_ASSERT_EQ(wp_data_addr, PC(write_data));
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@@ -239,7 +251,7 @@ static void guest_code(void)
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/* OS Lock blocking hardware-breakpoint */
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reset_debug_state();
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enable_os_lock();
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install_hw_bp(PC(hw_bp2));
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install_hw_bp(bpn, PC(hw_bp2));
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hw_bp_addr = 0;
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asm volatile("hw_bp2: nop");
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GUEST_ASSERT_EQ(hw_bp_addr, 0);
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@@ -251,7 +263,7 @@ static void guest_code(void)
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enable_os_lock();
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write_data = '\0';
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wp_data_addr = 0;
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install_wp(PC(write_data));
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install_wp(wpn, PC(write_data));
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write_data = 'x';
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GUEST_ASSERT_EQ(write_data, 'x');
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GUEST_ASSERT_EQ(wp_data_addr, 0);
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@@ -376,6 +388,8 @@ static void test_guest_debug_exceptions(void)
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vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT,
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ESR_EC_SVC64, guest_svc_handler);
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/* Run tests with breakpoint#0 and watchpoint#0. */
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vcpu_args_set(vcpu, 2, 0, 0);
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for (stage = 0; stage < 11; stage++) {
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vcpu_run(vcpu);
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