mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
synced 2026-04-18 03:23:53 -04:00
Merge tag 'drm-next-2023-10-31-1' of git://anongit.freedesktop.org/drm/drm
Pull drm updates from Dave Airlie:
"Highlights:
- AMD adds some more upcoming HW platforms
- Intel made Meteorlake stable and started adding Lunarlake
- nouveau has a bunch of display rework in prepartion for the NVIDIA
GSP firmware support
- msm adds a7xx support
- habanalabs has finished migration to accel subsystem
Detail summary:
kernel:
- add initial vmemdup-user-array
core:
- fix platform remove() to return void
- drm_file owner updated to reflect owner
- move size calcs to drm buddy allocator
- let GPUVM build as a module
- allow variable number of run-queues in scheduler
edid:
- handle bad h/v sync_end in EDIDs
panfrost:
- add Boris as maintainer
fbdev:
- use fb_ops helpers more
- only allow logo use from fbcon
- rename fb_pgproto to pgprot_framebuffer
- add HPD state to drm_connector_oob_hotplug_event
- convert to fbdev i/o mem helpers
i915:
- Enable meteorlake by default
- Early Xe2 LPD/Lunarlake display enablement
- Rework subplatforms into IP version checks
- GuC based TLB invalidation for Meteorlake
- Display rework for future Xe driver integration
- LNL FBC features
- LNL display feature capability reads
- update recommended fw versions for DG2+
- drop fastboot module parameter
- added deviceid for Arrowlake-S
- drop preproduction workarounds
- don't disable preemption for resets
- cleanup inlines in headers
- PXP firmware loading fix
- Fix sg list lengths
- DSC PPS state readout/verification
- Add more RPL P/U PCI IDs
- Add new DG2-G12 stepping
- DP enhanced framing support to state checker
- Improve shared link bandwidth management
- stop using GEM macros in display code
- refactor related code into display code
- locally enable W=1 warnings
- remove PSR watchdog timers on LNL
amdgpu:
- RAS/FRU EEPROM updatse
- IP discovery updatses
- GC 11.5 support
- DCN 3.5 support
- VPE 6.1 support
- NBIO 7.11 support
- DML2 support
- lots of IP updates
- use flexible arrays for bo list handling
- W=1 fixes
- Enable seamless boot in more cases
- Enable context type property for HDMI
- Rework GPUVM TLB flushing
- VCN IB start/size alignment fixes
amdkfd:
- GC 10/11 fixes
- GC 11.5 support
- use partial migration in GPU faults
radeon:
- W=1 Fixes
- fix some possible buffer overflow/NULL derefs
nouveau:
- update uapi for NO_PREFETCH
- scheduler/fence fixes
- rework suspend/resume for GSP-RM
- rework display in preparation for GSP-RM
habanalabs:
- uapi: expose tsc clock
- uapi: block access to eventfd through control device
- uapi: force dma-buf export to PAGE_SIZE alignments
- complete move to accel subsystem
- move firmware interface include files
- perform hard reset on PCIe AXI drain event
- optimise user interrupt handling
msm:
- DP: use existing helpers for DPCD
- DPU: interrupts reworked
- gpu: a7xx (a730/a740) support
- decouple msm_drv from kms for headless devices
mediatek:
- MT8188 dsi/dp/edp support
- DDP GAMMA - 12 bit LUT support
- connector dynamic selection capability
rockchip:
- rv1126 mipi-dsi/vop support
- add planar formats
ast:
- rename constants
panels:
- Mitsubishi AA084XE01
- JDI LPM102A188A
- LTK050H3148W-CTA6
ivpu:
- power management fixes
qaic:
- add detach slice bo api
komeda:
- add NV12 writeback
tegra:
- support NVSYNC/NHSYNC
- host1x suspend fixes
ili9882t:
- separate into own driver"
* tag 'drm-next-2023-10-31-1' of git://anongit.freedesktop.org/drm/drm: (1803 commits)
drm/amdgpu: Remove unused variables from amdgpu_show_fdinfo
drm/amdgpu: Remove duplicate fdinfo fields
drm/amd/amdgpu: avoid to disable gfxhub interrupt when driver is unloaded
drm/amdgpu: Add EXT_COHERENT support for APU and NUMA systems
drm/amdgpu: Retrieve CE count from ce_count_lo_chip in EccInfo table
drm/amdgpu: Identify data parity error corrected in replay mode
drm/amdgpu: Fix typo in IP discovery parsing
drm/amd/display: fix S/G display enablement
drm/amdxcp: fix amdxcp unloads incompletely
drm/amd/amdgpu: fix the GPU power print error in pm info
drm/amdgpu: Use pcie domain of xcc acpi objects
drm/amd: check num of link levels when update pcie param
drm/amdgpu: Add a read to GFX v9.4.3 ring test
drm/amd/pm: call smu_cmn_get_smc_version in is_mode1_reset_supported.
drm/amdgpu: get RAS poison status from DF v4_6_2
drm/amdgpu: Use discovery table's subrevision
drm/amd/display: 3.2.256
drm/amd/display: add interface to query SubVP status
drm/amd/display: Read before writing Backlight Mode Set Register
drm/amd/display: Disable SYMCLK32_SE RCO on DCN314
...
This commit is contained in:
Linus Torvalds
@@ -44,6 +44,7 @@
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* changes to accumulate
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*/
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#define AMDGPU_USERPTR_RESTORE_DELAY_MS 1
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#define AMDGPU_RESERVE_MEM_LIMIT (3UL << 29)
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/*
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* Align VRAM availability to 2MB to avoid fragmentation caused by 4K allocations in the tail 2MB
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@@ -117,11 +118,16 @@ void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
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return;
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si_meminfo(&si);
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mem = si.freeram - si.freehigh;
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mem = si.totalram - si.totalhigh;
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mem *= si.mem_unit;
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spin_lock_init(&kfd_mem_limit.mem_limit_lock);
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kfd_mem_limit.max_system_mem_limit = mem - (mem >> 4);
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kfd_mem_limit.max_system_mem_limit = mem - (mem >> 6);
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if (kfd_mem_limit.max_system_mem_limit < 2 * AMDGPU_RESERVE_MEM_LIMIT)
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kfd_mem_limit.max_system_mem_limit >>= 1;
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else
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kfd_mem_limit.max_system_mem_limit -= AMDGPU_RESERVE_MEM_LIMIT;
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kfd_mem_limit.max_ttm_mem_limit = ttm_tt_pages_limit() << PAGE_SHIFT;
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pr_debug("Kernel memory limit %lluM, TTM limit %lluM\n",
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(kfd_mem_limit.max_system_mem_limit >> 20),
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@@ -733,7 +739,7 @@ kfd_mem_dmaunmap_sg_bo(struct kgd_mem *mem,
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enum dma_data_direction dir;
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if (unlikely(!ttm->sg)) {
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pr_err("SG Table of BO is UNEXPECTEDLY NULL");
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pr_debug("SG Table of BO is NULL");
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return;
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}
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@@ -828,6 +834,7 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
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uint64_t va = mem->va;
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struct kfd_mem_attachment *attachment[2] = {NULL, NULL};
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struct amdgpu_bo *bo[2] = {NULL, NULL};
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struct amdgpu_bo_va *bo_va;
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bool same_hive = false;
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int i, ret;
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@@ -866,9 +873,10 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
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if ((adev == bo_adev && !(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) ||
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(amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && reuse_dmamap(adev, bo_adev)) ||
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same_hive) {
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(mem->domain == AMDGPU_GEM_DOMAIN_GTT && reuse_dmamap(adev, bo_adev)) ||
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same_hive) {
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/* Mappings on the local GPU, or VRAM mappings in the
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* local hive, or userptr mapping can reuse dma map
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* local hive, or userptr, or GTT mapping can reuse dma map
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* address space share the original BO
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*/
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attachment[i]->type = KFD_MEM_ATT_SHARED;
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@@ -914,7 +922,12 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
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pr_debug("Unable to reserve BO during memory attach");
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goto unwind;
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}
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attachment[i]->bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]);
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bo_va = amdgpu_vm_bo_find(vm, bo[i]);
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if (!bo_va)
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bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]);
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else
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++bo_va->ref_count;
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attachment[i]->bo_va = bo_va;
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amdgpu_bo_unreserve(bo[i]);
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if (unlikely(!attachment[i]->bo_va)) {
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ret = -ENOMEM;
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@@ -938,7 +951,8 @@ unwind:
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continue;
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if (attachment[i]->bo_va) {
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amdgpu_bo_reserve(bo[i], true);
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amdgpu_vm_bo_del(adev, attachment[i]->bo_va);
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if (--attachment[i]->bo_va->ref_count == 0)
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amdgpu_vm_bo_del(adev, attachment[i]->bo_va);
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amdgpu_bo_unreserve(bo[i]);
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list_del(&attachment[i]->list);
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}
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@@ -955,7 +969,8 @@ static void kfd_mem_detach(struct kfd_mem_attachment *attachment)
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pr_debug("\t remove VA 0x%llx in entry %p\n",
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attachment->va, attachment);
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amdgpu_vm_bo_del(attachment->adev, attachment->bo_va);
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if (--attachment->bo_va->ref_count == 0)
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amdgpu_vm_bo_del(attachment->adev, attachment->bo_va);
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drm_gem_object_put(&bo->tbo.base);
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list_del(&attachment->list);
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kfree(attachment);
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@@ -1201,8 +1216,6 @@ static void unmap_bo_from_gpuvm(struct kgd_mem *mem,
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amdgpu_vm_clear_freed(adev, vm, &bo_va->last_pt_update);
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amdgpu_sync_fence(sync, bo_va->last_pt_update);
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kfd_mem_dmaunmap_attachment(mem, entry);
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}
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static int update_gpuvm_pte(struct kgd_mem *mem,
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@@ -1257,6 +1270,7 @@ static int map_bo_to_gpuvm(struct kgd_mem *mem,
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update_gpuvm_pte_failed:
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unmap_bo_from_gpuvm(mem, entry, sync);
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kfd_mem_dmaunmap_attachment(mem, entry);
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return ret;
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}
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@@ -1690,6 +1704,8 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
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if (flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT)
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alloc_flags |= AMDGPU_GEM_CREATE_COHERENT;
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if (flags & KFD_IOC_ALLOC_MEM_FLAGS_EXT_COHERENT)
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alloc_flags |= AMDGPU_GEM_CREATE_EXT_COHERENT;
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if (flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED)
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alloc_flags |= AMDGPU_GEM_CREATE_UNCACHED;
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@@ -1860,8 +1876,10 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
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mem->va + bo_size * (1 + mem->aql_queue));
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/* Remove from VM internal data structures */
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list_for_each_entry_safe(entry, tmp, &mem->attachments, list)
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list_for_each_entry_safe(entry, tmp, &mem->attachments, list) {
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kfd_mem_dmaunmap_attachment(mem, entry);
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kfd_mem_detach(entry);
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}
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ret = unreserve_bo_and_vms(&ctx, false, false);
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@@ -2035,6 +2053,23 @@ out:
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return ret;
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}
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void amdgpu_amdkfd_gpuvm_dmaunmap_mem(struct kgd_mem *mem, void *drm_priv)
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{
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struct kfd_mem_attachment *entry;
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struct amdgpu_vm *vm;
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vm = drm_priv_to_vm(drm_priv);
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mutex_lock(&mem->lock);
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list_for_each_entry(entry, &mem->attachments, list) {
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if (entry->bo_va->base.vm == vm)
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kfd_mem_dmaunmap_attachment(mem, entry);
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}
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mutex_unlock(&mem->lock);
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}
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int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
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struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv)
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{
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