git/linux-cryptodev-2.6
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git synced 2026-04-25 00:52:45 -04:00
Code Issues Packages Projects Releases Wiki Activity

drm/amdgpu: add vcn v5_0_0 ip headers

Browse Source 
Add vcn v5_0_0 register offset and shift masks
header files
Only include the registers required for MMSCH
initialization

Signed-off-by: fanhuang <FangSheng.Huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
fanhuang
2025-05-06 14:49:18 +08:00
committed by Alex Deucher
parent 4ce5b99128
commit 80f66ca7a4
2 changed files with 39 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_offset.h
View File

@@ -1147,6 +1147,22 @@
#define regUVD_DPG_LMA_CTL2_BASE_IDX 1
// addressBlock: uvd_mmsch_dec
// base address: 0x20d2c
#define regMMSCH_VF_VMID 0x054b
#define regMMSCH_VF_VMID_BASE_IDX 1
#define regMMSCH_VF_CTX_ADDR_LO 0x054c
#define regMMSCH_VF_CTX_ADDR_LO_BASE_IDX 1
#define regMMSCH_VF_CTX_ADDR_HI 0x054d
#define regMMSCH_VF_CTX_ADDR_HI_BASE_IDX 1
#define regMMSCH_VF_CTX_SIZE 0x054e
#define regMMSCH_VF_CTX_SIZE_BASE_IDX 1
#define regMMSCH_VF_MAILBOX_HOST 0x0552
#define regMMSCH_VF_MAILBOX_HOST_BASE_IDX 1
#define regMMSCH_VF_MAILBOX_RESP 0x0553
#define regMMSCH_VF_MAILBOX_RESP_BASE_IDX 1
// addressBlock: uvd_vcn_umsch_dec
// base address: 0x21500
#define regVCN_UMSCH_MES_CNTL 0x0740

23
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h
View File

@@ -5929,6 +5929,29 @@
#define UVD_DPG_LMA_CTL2__JPEG_WRITE_PTR_MASK 0x0000FE00L
// addressBlock: uvd_mmsch_dec
//MMSCH_VF_VMID
#define MMSCH_VF_VMID__VF_CTX_VMID__SHIFT 0x0
#define MMSCH_VF_VMID__VF_GPCOM_VMID__SHIFT 0x5
#define MMSCH_VF_VMID__VF_CTX_VMID_MASK 0x0000001FL
#define MMSCH_VF_VMID__VF_GPCOM_VMID_MASK 0x000003E0L
//MMSCH_VF_CTX_ADDR_LO
#define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO__SHIFT 0x6
#define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO_MASK 0xFFFFFFC0L
//MMSCH_VF_CTX_ADDR_HI
#define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI__SHIFT 0x0
#define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI_MASK 0xFFFFFFFFL
//MMSCH_VF_CTX_SIZE
#define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE__SHIFT 0x0
#define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE_MASK 0xFFFFFFFFL
//MMSCH_VF_MAILBOX_HOST
#define MMSCH_VF_MAILBOX_HOST__DATA__SHIFT 0x0
#define MMSCH_VF_MAILBOX_HOST__DATA_MASK 0xFFFFFFFFL
//MMSCH_VF_MAILBOX_RESP
#define MMSCH_VF_MAILBOX_RESP__RESP__SHIFT 0x0
#define MMSCH_VF_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL
// addressBlock: uvd_vcn_umsch_dec
//VCN_UMSCH_MES_CNTL
#define VCN_UMSCH_MES_CNTL__PIPE_ID__SHIFT 0x0