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drm/gem: rename struct drm_gem_dma_object.{paddr => dma_addr}

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The field paddr of struct drm_gem_dma_object holds a DMA address, which
might actually be a physical address. However, depending on the platform,
it can also be a bus address or a virtual address managed by an IOMMU.

Hence, rename the field to dma_addr, which is more applicable.

In order to do this renaming the following coccinelle script was used:

```
	@@
	struct drm_gem_dma_object *gem;
	@@

	- gem->paddr
	+ gem->dma_addr

	@@
	struct drm_gem_dma_object gem;
	@@

	- gem.paddr
	+ gem.dma_addr

	@exists@
	typedef dma_addr_t;
	symbol paddr;
	@@

	dma_addr_t paddr;
	<...
	- paddr
	+ dma_addr
	...>

	@@
	symbol paddr;
	@@
	dma_addr_t
	- paddr
	+ dma_addr
	;

```

This patch is compile-time tested with:

```
	make ARCH={x86_64,arm,arm64} allyesconfig
	make ARCH={x86_64,arm,arm64} drivers/gpu/drm`
```

Acked-by: Sam Ravnborg <sam@ravnborg.org>
Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Danilo Krummrich <dakr@redhat.com>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20220802000405.949236-5-dakr@redhat.com
This commit is contained in:
Danilo Krummrich
2022-08-02 02:04:04 +02:00
committed by Sam Ravnborg
parent 4a83c26a1d
commit 8c30eecc67
39 changed files with 142 additions and 137 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/gpu/drm/vc4/vc4_validate.c
View File

@@ -294,7 +294,7 @@ validate_indexed_prim_list(VALIDATE_ARGS)
return -EINVAL;
}
*(uint32_t *)(validated + 5) = ib->paddr + offset;
*(uint32_t *)(validated + 5) = ib->dma_addr + offset;
return 0;
}
@@ -400,7 +400,7 @@ validate_tile_binning_config(VALIDATE_ARGS)
* free when the job completes rendering.
*/
exec->bin_slots |= BIT(bin_slot);
bin_addr = vc4->bin_bo->base.paddr + bin_slot * vc4->bin_alloc_size;
bin_addr = vc4->bin_bo->base.dma_addr + bin_slot * vc4->bin_alloc_size;
/* The tile state data array is 48 bytes per tile, and we put it at
* the start of a BO containing both it and the tile alloc.
@@ -608,7 +608,7 @@ reloc_tex(struct vc4_exec_info *exec,
"outside of UBO\n");
goto fail;
}
*validated_p0 = tex->paddr + p0;
*validated_p0 = tex->dma_addr + p0;
return true;
}
@@ -736,7 +736,7 @@ reloc_tex(struct vc4_exec_info *exec,
offset -= level_size;
}
*validated_p0 = tex->paddr + p0;
*validated_p0 = tex->dma_addr + p0;
if (is_cs) {
exec->bin_dep_seqno = max(exec->bin_dep_seqno,
@@ -840,7 +840,7 @@ validate_gl_shader_rec(struct drm_device *dev,
void *uniform_data_u;
uint32_t tex, uni;
*(uint32_t *)(pkt_v + o) = bo[i]->paddr + src_offset;
*(uint32_t *)(pkt_v + o) = bo[i]->dma_addr + src_offset;
if (src_offset != 0) {
DRM_DEBUG("Shaders must be at offset 0 of "
@@ -928,7 +928,7 @@ validate_gl_shader_rec(struct drm_device *dev,
}
}
*(uint32_t *)(pkt_v + o) = vbo->paddr + offset;
*(uint32_t *)(pkt_v + o) = vbo->dma_addr + offset;
}
return 0;