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https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
synced 2026-04-27 03:49:57 -04:00
drm/amd/pp: Revert gfx/compute profile switch sysfs
The gfx/compute profiling mode switch is only for internally test. Not a complete solution and unexpectly upstream. so revert it. Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu
@@ -3695,40 +3695,6 @@ static int ci_find_boot_level(struct ci_single_dpm_table *table,
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return ret;
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}
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static void ci_save_default_power_profile(struct amdgpu_device *adev)
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{
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struct ci_power_info *pi = ci_get_pi(adev);
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struct SMU7_Discrete_GraphicsLevel *levels =
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pi->smc_state_table.GraphicsLevel;
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uint32_t min_level = 0;
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pi->default_gfx_power_profile.activity_threshold =
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be16_to_cpu(levels[0].ActivityLevel);
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pi->default_gfx_power_profile.up_hyst = levels[0].UpH;
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pi->default_gfx_power_profile.down_hyst = levels[0].DownH;
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pi->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
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pi->default_compute_power_profile = pi->default_gfx_power_profile;
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pi->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
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/* Optimize compute power profile: Use only highest
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* 2 power levels (if more than 2 are available), Hysteresis:
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* 0ms up, 5ms down
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*/
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if (pi->smc_state_table.GraphicsDpmLevelCount > 2)
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min_level = pi->smc_state_table.GraphicsDpmLevelCount - 2;
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else if (pi->smc_state_table.GraphicsDpmLevelCount == 2)
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min_level = 1;
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pi->default_compute_power_profile.min_sclk =
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be32_to_cpu(levels[min_level].SclkFrequency);
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pi->default_compute_power_profile.up_hyst = 0;
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pi->default_compute_power_profile.down_hyst = 5;
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pi->gfx_power_profile = pi->default_gfx_power_profile;
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pi->compute_power_profile = pi->default_compute_power_profile;
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}
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static int ci_init_smc_table(struct amdgpu_device *adev)
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{
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struct ci_power_info *pi = ci_get_pi(adev);
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@@ -3874,8 +3840,6 @@ static int ci_init_smc_table(struct amdgpu_device *adev)
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if (ret)
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return ret;
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ci_save_default_power_profile(adev);
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return 0;
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}
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@@ -6753,222 +6717,6 @@ static int ci_dpm_set_mclk_od(void *handle, uint32_t value)
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return 0;
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}
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static int ci_dpm_get_power_profile_state(void *handle,
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struct amd_pp_profile *query)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct ci_power_info *pi = ci_get_pi(adev);
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if (!pi || !query)
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return -EINVAL;
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if (query->type == AMD_PP_GFX_PROFILE)
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memcpy(query, &pi->gfx_power_profile,
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sizeof(struct amd_pp_profile));
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else if (query->type == AMD_PP_COMPUTE_PROFILE)
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memcpy(query, &pi->compute_power_profile,
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sizeof(struct amd_pp_profile));
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else
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return -EINVAL;
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return 0;
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}
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static int ci_populate_requested_graphic_levels(struct amdgpu_device *adev,
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struct amd_pp_profile *request)
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{
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struct ci_power_info *pi = ci_get_pi(adev);
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struct ci_dpm_table *dpm_table = &(pi->dpm_table);
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struct SMU7_Discrete_GraphicsLevel *levels =
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pi->smc_state_table.GraphicsLevel;
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uint32_t array = pi->dpm_table_start +
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offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
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uint32_t array_size = sizeof(struct SMU7_Discrete_GraphicsLevel) *
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SMU7_MAX_LEVELS_GRAPHICS;
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uint32_t i;
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for (i = 0; i < dpm_table->sclk_table.count; i++) {
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levels[i].ActivityLevel =
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cpu_to_be16(request->activity_threshold);
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levels[i].EnabledForActivity = 1;
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levels[i].UpH = request->up_hyst;
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levels[i].DownH = request->down_hyst;
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}
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return amdgpu_ci_copy_bytes_to_smc(adev, array, (uint8_t *)levels,
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array_size, pi->sram_end);
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}
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static void ci_find_min_clock_masks(struct amdgpu_device *adev,
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uint32_t *sclk_mask, uint32_t *mclk_mask,
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uint32_t min_sclk, uint32_t min_mclk)
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{
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struct ci_power_info *pi = ci_get_pi(adev);
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struct ci_dpm_table *dpm_table = &(pi->dpm_table);
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uint32_t i;
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for (i = 0; i < dpm_table->sclk_table.count; i++) {
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if (dpm_table->sclk_table.dpm_levels[i].enabled &&
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dpm_table->sclk_table.dpm_levels[i].value >= min_sclk)
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*sclk_mask |= 1 << i;
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}
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for (i = 0; i < dpm_table->mclk_table.count; i++) {
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if (dpm_table->mclk_table.dpm_levels[i].enabled &&
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dpm_table->mclk_table.dpm_levels[i].value >= min_mclk)
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*mclk_mask |= 1 << i;
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}
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}
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static int ci_set_power_profile_state(struct amdgpu_device *adev,
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struct amd_pp_profile *request)
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{
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struct ci_power_info *pi = ci_get_pi(adev);
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int tmp_result, result = 0;
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uint32_t sclk_mask = 0, mclk_mask = 0;
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tmp_result = ci_freeze_sclk_mclk_dpm(adev);
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if (tmp_result) {
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DRM_ERROR("Failed to freeze SCLK MCLK DPM!");
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result = tmp_result;
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}
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tmp_result = ci_populate_requested_graphic_levels(adev,
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request);
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if (tmp_result) {
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DRM_ERROR("Failed to populate requested graphic levels!");
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result = tmp_result;
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}
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tmp_result = ci_unfreeze_sclk_mclk_dpm(adev);
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if (tmp_result) {
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DRM_ERROR("Failed to unfreeze SCLK MCLK DPM!");
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result = tmp_result;
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}
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ci_find_min_clock_masks(adev, &sclk_mask, &mclk_mask,
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request->min_sclk, request->min_mclk);
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if (sclk_mask) {
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if (!pi->sclk_dpm_key_disabled)
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amdgpu_ci_send_msg_to_smc_with_parameter(
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adev,
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PPSMC_MSG_SCLKDPM_SetEnabledMask,
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pi->dpm_level_enable_mask.
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sclk_dpm_enable_mask &
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sclk_mask);
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}
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if (mclk_mask) {
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if (!pi->mclk_dpm_key_disabled)
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amdgpu_ci_send_msg_to_smc_with_parameter(
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adev,
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PPSMC_MSG_MCLKDPM_SetEnabledMask,
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pi->dpm_level_enable_mask.
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mclk_dpm_enable_mask &
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mclk_mask);
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}
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return result;
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}
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static int ci_dpm_set_power_profile_state(void *handle,
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struct amd_pp_profile *request)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct ci_power_info *pi = ci_get_pi(adev);
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int ret = -1;
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if (!pi || !request)
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return -EINVAL;
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if (adev->pm.dpm.forced_level !=
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AMD_DPM_FORCED_LEVEL_AUTO)
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return -EINVAL;
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if (request->min_sclk ||
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request->min_mclk ||
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request->activity_threshold ||
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request->up_hyst ||
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request->down_hyst) {
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if (request->type == AMD_PP_GFX_PROFILE)
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memcpy(&pi->gfx_power_profile, request,
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sizeof(struct amd_pp_profile));
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else if (request->type == AMD_PP_COMPUTE_PROFILE)
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memcpy(&pi->compute_power_profile, request,
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sizeof(struct amd_pp_profile));
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else
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return -EINVAL;
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if (request->type == pi->current_power_profile)
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ret = ci_set_power_profile_state(
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adev,
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request);
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} else {
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/* set power profile if it exists */
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switch (request->type) {
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case AMD_PP_GFX_PROFILE:
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ret = ci_set_power_profile_state(
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adev,
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&pi->gfx_power_profile);
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break;
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case AMD_PP_COMPUTE_PROFILE:
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ret = ci_set_power_profile_state(
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adev,
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&pi->compute_power_profile);
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break;
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default:
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return -EINVAL;
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}
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}
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if (!ret)
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pi->current_power_profile = request->type;
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return 0;
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}
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static int ci_dpm_reset_power_profile_state(void *handle,
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struct amd_pp_profile *request)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct ci_power_info *pi = ci_get_pi(adev);
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if (!pi || !request)
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return -EINVAL;
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if (request->type == AMD_PP_GFX_PROFILE) {
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pi->gfx_power_profile = pi->default_gfx_power_profile;
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return ci_dpm_set_power_profile_state(adev,
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&pi->gfx_power_profile);
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} else if (request->type == AMD_PP_COMPUTE_PROFILE) {
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pi->compute_power_profile =
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pi->default_compute_power_profile;
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return ci_dpm_set_power_profile_state(adev,
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&pi->compute_power_profile);
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} else
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return -EINVAL;
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}
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static int ci_dpm_switch_power_profile(void *handle,
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enum amd_pp_profile_type type)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct ci_power_info *pi = ci_get_pi(adev);
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struct amd_pp_profile request = {0};
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if (!pi)
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return -EINVAL;
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if (pi->current_power_profile != type) {
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request.type = type;
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return ci_dpm_set_power_profile_state(adev, &request);
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}
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return 0;
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}
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static int ci_dpm_read_sensor(void *handle, int idx,
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void *value, int *size)
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{
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@@ -7053,10 +6801,6 @@ const struct amd_pm_funcs ci_dpm_funcs = {
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.set_mclk_od = ci_dpm_set_mclk_od,
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.check_state_equal = ci_check_state_equal,
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.get_vce_clock_state = amdgpu_get_vce_clock_state,
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.get_power_profile_state = ci_dpm_get_power_profile_state,
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.set_power_profile_state = ci_dpm_set_power_profile_state,
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.reset_power_profile_state = ci_dpm_reset_power_profile_state,
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.switch_power_profile = ci_dpm_switch_power_profile,
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.read_sensor = ci_dpm_read_sensor,
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};
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