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drm/amd/display: Make DMCUB bss/data firmware blob optional

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[Why]
By moving everything out of .data into the other regions we can drop
the requirement for the second blob and unify it all into the inst/const
blob.

[How]
We need to still support the blob being there and not being there for
backwards compatibility.

Look for the DMCUB metadata section in the end of the inst/const blob
instead of bss/data is missing.

Clear CW2 if we don't have the data blob so we don't hang when
transitioning between data blob/blobless firmwares.

Don't memcpy the blob into CW2 region if it doesn't exist.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Nicholas Kazlauskas
2020-04-05 16:41:14 -04:00
committed by Alex Deucher
parent 8ccf0e2076
commit a576b345f9
4 changed files with 40 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
View File

@@ -186,14 +186,22 @@ void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
dmub_dcn20_get_fb_base_offset(dmub, &fb_base, &fb_offset);
dmub_dcn20_translate_addr(&cw2->offset, fb_base, fb_offset, &offset);
if (cw2->region.base != cw2->region.top) {
dmub_dcn20_translate_addr(&cw2->offset, fb_base, fb_offset,
&offset);
REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part);
REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part);
REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base);
REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0,
DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top,
DMCUB_REGION3_CW2_ENABLE, 1);
REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part);
REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part);
REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base);
REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0,
DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top,
DMCUB_REGION3_CW2_ENABLE, 1);
} else {
REG_WRITE(DMCUB_REGION3_CW2_OFFSET, 0);
REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, 0);
REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, 0);
REG_WRITE(DMCUB_REGION3_CW2_TOP_ADDRESS, 0);
}
dmub_dcn20_translate_addr(&cw3->offset, fb_base, fb_offset, &offset);