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drm/nouveau/fifo: switch to instanced constructor

Browse Source 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
This commit is contained in:
Ben Skeggs
2020-12-04 15:29:16 +10:00
parent 09f409d74d
commit ab0db2bd85
28 changed files with 171 additions and 161 deletions
Download Patch File Download Diff File Expand all files Collapse all files

167
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@@ -90,7 +90,7 @@ nv4_chipset = {
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv04_fifo_new,
.fifo = { 0x00000001, nv04_fifo_new },
.gr = nv04_gr_new,
.sw = nv04_sw_new,
};
@@ -111,7 +111,7 @@ nv5_chipset = {
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv04_fifo_new,
.fifo = { 0x00000001, nv04_fifo_new },
.gr = nv04_gr_new,
.sw = nv04_sw_new,
};
@@ -153,7 +153,7 @@ nv11_chipset = {
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv10_fifo_new,
.fifo = { 0x00000001, nv10_fifo_new },
.gr = nv15_gr_new,
.sw = nv10_sw_new,
};
@@ -175,7 +175,7 @@ nv15_chipset = {
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv10_fifo_new,
.fifo = { 0x00000001, nv10_fifo_new },
.gr = nv15_gr_new,
.sw = nv10_sw_new,
};
@@ -197,7 +197,7 @@ nv17_chipset = {
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv17_fifo_new,
.fifo = { 0x00000001, nv17_fifo_new },
.gr = nv17_gr_new,
.sw = nv10_sw_new,
};
@@ -219,7 +219,7 @@ nv18_chipset = {
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv17_fifo_new,
.fifo = { 0x00000001, nv17_fifo_new },
.gr = nv17_gr_new,
.sw = nv10_sw_new,
};
@@ -241,7 +241,7 @@ nv1a_chipset = {
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv10_fifo_new,
.fifo = { 0x00000001, nv10_fifo_new },
.gr = nv15_gr_new,
.sw = nv10_sw_new,
};
@@ -263,7 +263,7 @@ nv1f_chipset = {
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv17_fifo_new,
.fifo = { 0x00000001, nv17_fifo_new },
.gr = nv17_gr_new,
.sw = nv10_sw_new,
};
@@ -285,7 +285,7 @@ nv20_chipset = {
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv17_fifo_new,
.fifo = { 0x00000001, nv17_fifo_new },
.gr = nv20_gr_new,
.sw = nv10_sw_new,
};
@@ -307,7 +307,7 @@ nv25_chipset = {
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv17_fifo_new,
.fifo = { 0x00000001, nv17_fifo_new },
.gr = nv25_gr_new,
.sw = nv10_sw_new,
};
@@ -329,7 +329,7 @@ nv28_chipset = {
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv17_fifo_new,
.fifo = { 0x00000001, nv17_fifo_new },
.gr = nv25_gr_new,
.sw = nv10_sw_new,
};
@@ -351,7 +351,7 @@ nv2a_chipset = {
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv17_fifo_new,
.fifo = { 0x00000001, nv17_fifo_new },
.gr = nv2a_gr_new,
.sw = nv10_sw_new,
};
@@ -373,7 +373,7 @@ nv30_chipset = {
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv17_fifo_new,
.fifo = { 0x00000001, nv17_fifo_new },
.gr = nv30_gr_new,
.sw = nv10_sw_new,
};
@@ -395,7 +395,7 @@ nv31_chipset = {
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv17_fifo_new,
.fifo = { 0x00000001, nv17_fifo_new },
.gr = nv30_gr_new,
.mpeg = nv31_mpeg_new,
.sw = nv10_sw_new,
@@ -418,7 +418,7 @@ nv34_chipset = {
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv17_fifo_new,
.fifo = { 0x00000001, nv17_fifo_new },
.gr = nv34_gr_new,
.mpeg = nv31_mpeg_new,
.sw = nv10_sw_new,
@@ -441,7 +441,7 @@ nv35_chipset = {
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv17_fifo_new,
.fifo = { 0x00000001, nv17_fifo_new },
.gr = nv35_gr_new,
.sw = nv10_sw_new,
};
@@ -463,7 +463,7 @@ nv36_chipset = {
.timer = { 0x00000001, nv04_timer_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv17_fifo_new,
.fifo = { 0x00000001, nv17_fifo_new },
.gr = nv35_gr_new,
.mpeg = nv31_mpeg_new,
.sw = nv10_sw_new,
@@ -488,7 +488,7 @@ nv40_chipset = {
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv40_gr_new,
.mpeg = nv40_mpeg_new,
.pm = nv40_pm_new,
@@ -514,7 +514,7 @@ nv41_chipset = {
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv40_gr_new,
.mpeg = nv40_mpeg_new,
.pm = nv40_pm_new,
@@ -540,7 +540,7 @@ nv42_chipset = {
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv40_gr_new,
.mpeg = nv40_mpeg_new,
.pm = nv40_pm_new,
@@ -566,7 +566,7 @@ nv43_chipset = {
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv40_gr_new,
.mpeg = nv40_mpeg_new,
.pm = nv40_pm_new,
@@ -592,7 +592,7 @@ nv44_chipset = {
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv44_gr_new,
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
@@ -618,7 +618,7 @@ nv45_chipset = {
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv40_gr_new,
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
@@ -644,7 +644,7 @@ nv46_chipset = {
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv44_gr_new,
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
@@ -670,7 +670,7 @@ nv47_chipset = {
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv40_gr_new,
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
@@ -696,7 +696,7 @@ nv49_chipset = {
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv40_gr_new,
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
@@ -722,7 +722,7 @@ nv4a_chipset = {
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv44_gr_new,
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
@@ -748,7 +748,7 @@ nv4b_chipset = {
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv40_gr_new,
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
@@ -774,7 +774,7 @@ nv4c_chipset = {
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv44_gr_new,
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
@@ -800,7 +800,7 @@ nv4e_chipset = {
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv44_gr_new,
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
@@ -829,7 +829,7 @@ nv50_chipset = {
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv50_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = nv50_fifo_new,
.fifo = { 0x00000001, nv50_fifo_new },
.gr = nv50_gr_new,
.mpeg = nv50_mpeg_new,
.pm = nv50_pm_new,
@@ -855,7 +855,7 @@ nv63_chipset = {
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv44_gr_new,
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
@@ -881,7 +881,7 @@ nv67_chipset = {
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv44_gr_new,
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
@@ -907,7 +907,7 @@ nv68_chipset = {
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, nv04_disp_new },
.dma = { 0x00000001, nv04_dma_new },
.fifo = nv40_fifo_new,
.fifo = { 0x00000001, nv40_fifo_new },
.gr = nv44_gr_new,
.mpeg = nv44_mpeg_new,
.pm = nv40_pm_new,
@@ -938,7 +938,7 @@ nv84_chipset = {
.cipher = { 0x00000001, g84_cipher_new },
.disp = { 0x00000001, g84_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = g84_fifo_new,
.fifo = { 0x00000001, g84_fifo_new },
.gr = g84_gr_new,
.mpeg = g84_mpeg_new,
.pm = g84_pm_new,
@@ -970,7 +970,7 @@ nv86_chipset = {
.cipher = { 0x00000001, g84_cipher_new },
.disp = { 0x00000001, g84_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = g84_fifo_new,
.fifo = { 0x00000001, g84_fifo_new },
.gr = g84_gr_new,
.mpeg = g84_mpeg_new,
.pm = g84_pm_new,
@@ -1002,7 +1002,7 @@ nv92_chipset = {
.cipher = { 0x00000001, g84_cipher_new },
.disp = { 0x00000001, g84_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = g84_fifo_new,
.fifo = { 0x00000001, g84_fifo_new },
.gr = g84_gr_new,
.mpeg = g84_mpeg_new,
.pm = g84_pm_new,
@@ -1034,7 +1034,7 @@ nv94_chipset = {
.cipher = { 0x00000001, g84_cipher_new },
.disp = { 0x00000001, g94_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = g84_fifo_new,
.fifo = { 0x00000001, g84_fifo_new },
.gr = g84_gr_new,
.mpeg = g84_mpeg_new,
.pm = g84_pm_new,
@@ -1066,7 +1066,7 @@ nv96_chipset = {
.cipher = { 0x00000001, g84_cipher_new },
.disp = { 0x00000001, g94_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = g84_fifo_new,
.fifo = { 0x00000001, g84_fifo_new },
.gr = g84_gr_new,
.mpeg = g84_mpeg_new,
.pm = g84_pm_new,
@@ -1096,7 +1096,7 @@ nv98_chipset = {
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, g94_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = g84_fifo_new,
.fifo = { 0x00000001, g84_fifo_new },
.gr = g84_gr_new,
.mspdec = g98_mspdec_new,
.msppp = g98_msppp_new,
@@ -1130,7 +1130,7 @@ nva0_chipset = {
.cipher = { 0x00000001, g84_cipher_new },
.disp = { 0x00000001, gt200_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = g84_fifo_new,
.fifo = { 0x00000001, g84_fifo_new },
.gr = gt200_gr_new,
.mpeg = g84_mpeg_new,
.pm = gt200_pm_new,
@@ -1162,7 +1162,7 @@ nva3_chipset = {
.ce = { 0x00000001, gt215_ce_new },
.disp = { 0x00000001, gt215_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = g84_fifo_new,
.fifo = { 0x00000001, g84_fifo_new },
.gr = gt215_gr_new,
.mpeg = g84_mpeg_new,
.mspdec = gt215_mspdec_new,
@@ -1196,7 +1196,7 @@ nva5_chipset = {
.ce = { 0x00000001, gt215_ce_new },
.disp = { 0x00000001, gt215_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = g84_fifo_new,
.fifo = { 0x00000001, g84_fifo_new },
.gr = gt215_gr_new,
.mspdec = gt215_mspdec_new,
.msppp = gt215_msppp_new,
@@ -1229,7 +1229,7 @@ nva8_chipset = {
.ce = { 0x00000001, gt215_ce_new },
.disp = { 0x00000001, gt215_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = g84_fifo_new,
.fifo = { 0x00000001, g84_fifo_new },
.gr = gt215_gr_new,
.mspdec = gt215_mspdec_new,
.msppp = gt215_msppp_new,
@@ -1260,7 +1260,7 @@ nvaa_chipset = {
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, mcp77_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = g84_fifo_new,
.fifo = { 0x00000001, g84_fifo_new },
.gr = gt200_gr_new,
.mspdec = g98_mspdec_new,
.msppp = g98_msppp_new,
@@ -1292,7 +1292,7 @@ nvac_chipset = {
.volt = { 0x00000001, nv40_volt_new },
.disp = { 0x00000001, mcp77_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = g84_fifo_new,
.fifo = { 0x00000001, g84_fifo_new },
.gr = mcp79_gr_new,
.mspdec = g98_mspdec_new,
.msppp = g98_msppp_new,
@@ -1326,7 +1326,7 @@ nvaf_chipset = {
.ce = { 0x00000001, gt215_ce_new },
.disp = { 0x00000001, mcp89_disp_new },
.dma = { 0x00000001, nv50_dma_new },
.fifo = g84_fifo_new,
.fifo = { 0x00000001, g84_fifo_new },
.gr = mcp89_gr_new,
.mspdec = gt215_mspdec_new,
.msppp = gt215_msppp_new,
@@ -1362,7 +1362,7 @@ nvc0_chipset = {
.ce = { 0x00000003, gf100_ce_new },
.disp = { 0x00000001, gt215_disp_new },
.dma = { 0x00000001, gf100_dma_new },
.fifo = gf100_fifo_new,
.fifo = { 0x00000001, gf100_fifo_new },
.gr = gf100_gr_new,
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
@@ -1398,7 +1398,7 @@ nvc1_chipset = {
.ce = { 0x00000001, gf100_ce_new },
.disp = { 0x00000001, gt215_disp_new },
.dma = { 0x00000001, gf100_dma_new },
.fifo = gf100_fifo_new,
.fifo = { 0x00000001, gf100_fifo_new },
.gr = gf108_gr_new,
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
@@ -1434,7 +1434,7 @@ nvc3_chipset = {
.ce = { 0x00000001, gf100_ce_new },
.disp = { 0x00000001, gt215_disp_new },
.dma = { 0x00000001, gf100_dma_new },
.fifo = gf100_fifo_new,
.fifo = { 0x00000001, gf100_fifo_new },
.gr = gf104_gr_new,
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
@@ -1470,7 +1470,7 @@ nvc4_chipset = {
.ce = { 0x00000003, gf100_ce_new },
.disp = { 0x00000001, gt215_disp_new },
.dma = { 0x00000001, gf100_dma_new },
.fifo = gf100_fifo_new,
.fifo = { 0x00000001, gf100_fifo_new },
.gr = gf104_gr_new,
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
@@ -1506,7 +1506,7 @@ nvc8_chipset = {
.ce = { 0x00000003, gf100_ce_new },
.disp = { 0x00000001, gt215_disp_new },
.dma = { 0x00000001, gf100_dma_new },
.fifo = gf100_fifo_new,
.fifo = { 0x00000001, gf100_fifo_new },
.gr = gf110_gr_new,
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
@@ -1542,7 +1542,7 @@ nvce_chipset = {
.ce = { 0x00000003, gf100_ce_new },
.disp = { 0x00000001, gt215_disp_new },
.dma = { 0x00000001, gf100_dma_new },
.fifo = gf100_fifo_new,
.fifo = { 0x00000001, gf100_fifo_new },
.gr = gf104_gr_new,
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
@@ -1578,7 +1578,7 @@ nvcf_chipset = {
.ce = { 0x00000001, gf100_ce_new },
.disp = { 0x00000001, gt215_disp_new },
.dma = { 0x00000001, gf100_dma_new },
.fifo = gf100_fifo_new,
.fifo = { 0x00000001, gf100_fifo_new },
.gr = gf104_gr_new,
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
@@ -1613,7 +1613,7 @@ nvd7_chipset = {
.ce = { 0x00000001, gf100_ce_new },
.disp = { 0x00000001, gf119_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = gf100_fifo_new,
.fifo = { 0x00000001, gf100_fifo_new },
.gr = gf117_gr_new,
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
@@ -1649,7 +1649,7 @@ nvd9_chipset = {
.ce = { 0x00000001, gf100_ce_new },
.disp = { 0x00000001, gf119_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = gf100_fifo_new,
.fifo = { 0x00000001, gf100_fifo_new },
.gr = gf119_gr_new,
.mspdec = gf100_mspdec_new,
.msppp = gf100_msppp_new,
@@ -1686,7 +1686,7 @@ nve4_chipset = {
.ce = { 0x00000007, gk104_ce_new },
.disp = { 0x00000001, gk104_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = gk104_fifo_new,
.fifo = { 0x00000001, gk104_fifo_new },
.gr = gk104_gr_new,
.mspdec = gk104_mspdec_new,
.msppp = gf100_msppp_new,
@@ -1723,7 +1723,7 @@ nve6_chipset = {
.ce = { 0x00000007, gk104_ce_new },
.disp = { 0x00000001, gk104_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = gk104_fifo_new,
.fifo = { 0x00000001, gk104_fifo_new },
.gr = gk104_gr_new,
.mspdec = gk104_mspdec_new,
.msppp = gf100_msppp_new,
@@ -1760,7 +1760,7 @@ nve7_chipset = {
.ce = { 0x00000007, gk104_ce_new },
.disp = { 0x00000001, gk104_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = gk104_fifo_new,
.fifo = { 0x00000001, gk104_fifo_new },
.gr = gk104_gr_new,
.mspdec = gk104_mspdec_new,
.msppp = gf100_msppp_new,
@@ -1788,7 +1788,7 @@ nvea_chipset = {
.volt = { 0x00000001, gk20a_volt_new },
.ce = { 0x00000004, gk104_ce_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = gk20a_fifo_new,
.fifo = { 0x00000001, gk20a_fifo_new },
.gr = gk20a_gr_new,
.pm = gk104_pm_new,
.sw = gf100_sw_new,
@@ -1822,7 +1822,7 @@ nvf0_chipset = {
.ce = { 0x00000007, gk104_ce_new },
.disp = { 0x00000001, gk110_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = gk110_fifo_new,
.fifo = { 0x00000001, gk110_fifo_new },
.gr = gk110_gr_new,
.mspdec = gk104_mspdec_new,
.msppp = gf100_msppp_new,
@@ -1858,7 +1858,7 @@ nvf1_chipset = {
.ce = { 0x00000007, gk104_ce_new },
.disp = { 0x00000001, gk110_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = gk110_fifo_new,
.fifo = { 0x00000001, gk110_fifo_new },
.gr = gk110b_gr_new,
.mspdec = gk104_mspdec_new,
.msppp = gf100_msppp_new,
@@ -1894,7 +1894,7 @@ nv106_chipset = {
.ce = { 0x00000007, gk104_ce_new },
.disp = { 0x00000001, gk110_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = gk208_fifo_new,
.fifo = { 0x00000001, gk208_fifo_new },
.gr = gk208_gr_new,
.mspdec = gk104_mspdec_new,
.msppp = gf100_msppp_new,
@@ -1930,7 +1930,7 @@ nv108_chipset = {
.ce = { 0x00000007, gk104_ce_new },
.disp = { 0x00000001, gk110_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = gk208_fifo_new,
.fifo = { 0x00000001, gk208_fifo_new },
.gr = gk208_gr_new,
.mspdec = gk104_mspdec_new,
.msppp = gf100_msppp_new,
@@ -1966,7 +1966,7 @@ nv117_chipset = {
.ce = { 0x00000005, gm107_ce_new },
.disp = { 0x00000001, gm107_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = gm107_fifo_new,
.fifo = { 0x00000001, gm107_fifo_new },
.gr = gm107_gr_new,
.nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new,
@@ -2001,7 +2001,7 @@ nv118_chipset = {
.ce = { 0x00000005, gm107_ce_new },
.disp = { 0x00000001, gm107_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = gm107_fifo_new,
.fifo = { 0x00000001, gm107_fifo_new },
.gr = gm107_gr_new,
.sw = gf100_sw_new,
};
@@ -2034,7 +2034,7 @@ nv120_chipset = {
.ce = { 0x00000007, gm200_ce_new },
.disp = { 0x00000001, gm200_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = gm200_fifo_new,
.fifo = { 0x00000001, gm200_fifo_new },
.gr = gm200_gr_new,
.nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new,
@@ -2070,7 +2070,7 @@ nv124_chipset = {
.ce = { 0x00000007, gm200_ce_new },
.disp = { 0x00000001, gm200_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = gm200_fifo_new,
.fifo = { 0x00000001, gm200_fifo_new },
.gr = gm200_gr_new,
.nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new,
@@ -2106,7 +2106,7 @@ nv126_chipset = {
.ce = { 0x00000007, gm200_ce_new },
.disp = { 0x00000001, gm200_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = gm200_fifo_new,
.fifo = { 0x00000001, gm200_fifo_new },
.gr = gm200_gr_new,
.nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new,
@@ -2133,7 +2133,7 @@ nv12b_chipset = {
.volt = { 0x00000001, gm20b_volt_new },
.ce = { 0x00000004, gm200_ce_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = gm20b_fifo_new,
.fifo = { 0x00000001, gm20b_fifo_new },
.gr = gm20b_gr_new,
.sw = gf100_sw_new,
};
@@ -2164,7 +2164,7 @@ nv130_chipset = {
.ce = { 0x0000003f, gp100_ce_new },
.dma = { 0x00000001, gf119_dma_new },
.disp = { 0x00000001, gp100_disp_new },
.fifo = gp100_fifo_new,
.fifo = { 0x00000001, gp100_fifo_new },
.gr = gp100_gr_new,
.nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new,
@@ -2199,7 +2199,7 @@ nv132_chipset = {
.ce = { 0x0000000f, gp102_ce_new },
.disp = { 0x00000001, gp102_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = gp100_fifo_new,
.fifo = { 0x00000001, gp100_fifo_new },
.gr = gp102_gr_new,
.nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new,
@@ -2234,7 +2234,7 @@ nv134_chipset = {
.ce = { 0x0000000f, gp102_ce_new },
.disp = { 0x00000001, gp102_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = gp100_fifo_new,
.fifo = { 0x00000001, gp100_fifo_new },
.gr = gp104_gr_new,
.nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new,
@@ -2269,7 +2269,7 @@ nv136_chipset = {
.ce = { 0x0000000f, gp102_ce_new },
.disp = { 0x00000001, gp102_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = gp100_fifo_new,
.fifo = { 0x00000001, gp100_fifo_new },
.gr = gp104_gr_new,
.nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new,
@@ -2303,7 +2303,7 @@ nv137_chipset = {
.ce = { 0x0000000f, gp102_ce_new },
.disp = { 0x00000001, gp102_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = gp100_fifo_new,
.fifo = { 0x00000001, gp100_fifo_new },
.gr = gp107_gr_new,
.nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new,
@@ -2338,7 +2338,7 @@ nv138_chipset = {
.ce = { 0x0000000f, gp102_ce_new },
.disp = { 0x00000001, gp102_disp_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = gp100_fifo_new,
.fifo = { 0x00000001, gp100_fifo_new },
.gr = gp108_gr_new,
.nvdec[0] = gm107_nvdec_new,
.sec2 = gp108_sec2_new,
@@ -2364,7 +2364,7 @@ nv13b_chipset = {
.top = { 0x00000001, gk104_top_new },
.ce = { 0x00000001, gp100_ce_new },
.dma = { 0x00000001, gf119_dma_new },
.fifo = gp10b_fifo_new,
.fifo = { 0x00000001, gp10b_fifo_new },
.gr = gp10b_gr_new,
.sw = gf100_sw_new,
};
@@ -2396,7 +2396,7 @@ nv140_chipset = {
.ce = { 0x000001ff, gv100_ce_new },
.disp = { 0x00000001, gv100_disp_new },
.dma = { 0x00000001, gv100_dma_new },
.fifo = gv100_fifo_new,
.fifo = { 0x00000001, gv100_fifo_new },
.gr = gv100_gr_new,
.nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new,
@@ -2432,7 +2432,7 @@ nv162_chipset = {
.ce = { 0x0000001f, tu102_ce_new },
.disp = { 0x00000001, tu102_disp_new },
.dma = { 0x00000001, gv100_dma_new },
.fifo = tu102_fifo_new,
.fifo = { 0x00000001, tu102_fifo_new },
.gr = tu102_gr_new,
.nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new,
@@ -2466,7 +2466,7 @@ nv164_chipset = {
.ce = { 0x0000001f, tu102_ce_new },
.disp = { 0x00000001, tu102_disp_new },
.dma = { 0x00000001, gv100_dma_new },
.fifo = tu102_fifo_new,
.fifo = { 0x00000001, tu102_fifo_new },
.gr = tu102_gr_new,
.nvdec[0] = gm107_nvdec_new,
.nvdec[1] = gm107_nvdec_new,
@@ -2501,7 +2501,7 @@ nv166_chipset = {
.ce = { 0x0000001f, tu102_ce_new },
.disp = { 0x00000001, tu102_disp_new },
.dma = { 0x00000001, gv100_dma_new },
.fifo = tu102_fifo_new,
.fifo = { 0x00000001, tu102_fifo_new },
.gr = tu102_gr_new,
.nvdec[0] = gm107_nvdec_new,
.nvdec[1] = gm107_nvdec_new,
@@ -2537,7 +2537,7 @@ nv167_chipset = {
.ce = { 0x0000001f, tu102_ce_new },
.disp = { 0x00000001, tu102_disp_new },
.dma = { 0x00000001, gv100_dma_new },
.fifo = tu102_fifo_new,
.fifo = { 0x00000001, tu102_fifo_new },
.gr = tu102_gr_new,
.nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new,
@@ -2571,7 +2571,7 @@ nv168_chipset = {
.ce = { 0x0000001f, tu102_ce_new },
.disp = { 0x00000001, tu102_disp_new },
.dma = { 0x00000001, gv100_dma_new },
.fifo = tu102_fifo_new,
.fifo = { 0x00000001, tu102_fifo_new },
.gr = tu102_gr_new,
.nvdec[0] = gm107_nvdec_new,
.nvenc[0] = gm107_nvenc_new,
@@ -3174,7 +3174,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
#include <core/layout.h>
#undef NVKM_LAYOUT_INST
#undef NVKM_LAYOUT_ONCE
_(NVKM_ENGINE_FIFO , fifo);
_(NVKM_ENGINE_GR , gr);
_(NVKM_ENGINE_IFB , ifb);
_(NVKM_ENGINE_ME , me);