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drm/amdgpu: fix the hang caused by PCIe link width switch

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SMU had set all the necessary fields for a link width switch
but the width switch wasn't occurring because the link was idle
in the L1 state. Setting LC_L1_RECONFIG_EN=0x1 will allow width
switches to also be initiated while in L1 instead of waiting until
the link is back in L0.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
This commit is contained in:
Evan Quan
2021-05-25 14:36:29 +08:00
committed by Alex Deucher
parent 5a5da8ae95
commit adcf949e66
3 changed files with 17 additions and 0 deletions
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3
drivers/gpu/drm/amd/amdgpu/nv.c
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@@ -1414,6 +1414,9 @@ static int nv_common_hw_init(void *handle)
if (adev->nbio.funcs->apply_lc_spc_mode_wa)
adev->nbio.funcs->apply_lc_spc_mode_wa(adev);
if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa)
adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev);
/* enable pcie gen2/3 link */
nv_pcie_gen3_enable(adev);
/* enable aspm */