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drm/amd/display: Revert "Fix clock table filling logic"

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[Why]
This change was found to break some high-refresh modes. Reverting
to unblock mainline.

Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Reviewed-by: Sung Lee <Sung.Lee@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Ilya Bakoulin
2021-05-18 17:55:17 -04:00
committed by Alex Deucher
parent 24cc4f8d7b
commit ae88357c79
2 changed files with 45 additions and 78 deletions
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33
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
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@@ -1575,12 +1575,10 @@ static struct _vcs_dpi_voltage_scaling_st construct_low_pstate_lvl(struct clk_li
low_pstate_lvl.phyclk_d18_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_d18_mhz;
low_pstate_lvl.phyclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_mhz;
if (clk_table->num_entries < MAX_NUM_DPM_LVL) {
for (i = clk_table->num_entries; i > 1; i--)
clk_table->entries[i] = clk_table->entries[i-1];
clk_table->entries[1] = clk_table->entries[0];
clk_table->num_entries++;
}
for (i = clk_table->num_entries; i > 1; i--)
clk_table->entries[i] = clk_table->entries[i-1];
clk_table->entries[1] = clk_table->entries[0];
clk_table->num_entries++;
return low_pstate_lvl;
}
@@ -1612,6 +1610,10 @@ static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
}
}
/* clk_table[1] is reserved for min DF PState. skip here to fill in later. */
if (i == 1)
k++;
clock_limits[k].state = k;
clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
@@ -1628,25 +1630,14 @@ static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
k++;
}
if (clk_table->num_entries >= MAX_NUM_DPM_LVL) {
for (i = 0; i < clk_table->num_entries + 1; i++)
dcn2_1_soc.clock_limits[i] = clock_limits[i];
} else {
dcn2_1_soc.clock_limits[0] = clock_limits[0];
for (i = 2; i < clk_table->num_entries + 1; i++) {
dcn2_1_soc.clock_limits[i] = clock_limits[i - 1];
dcn2_1_soc.clock_limits[i].state = i;
}
}
for (i = 0; i < clk_table->num_entries + 1; i++)
dcn2_1_soc.clock_limits[i] = clock_limits[i];
if (clk_table->num_entries) {
dcn2_1_soc.num_states = clk_table->num_entries + 1;
/* fill in min DF PState */
dcn2_1_soc.clock_limits[1] = construct_low_pstate_lvl(clk_table, closest_clk_lvl);
dcn2_1_soc.num_states = clk_table->num_entries;
/* duplicate last level */
dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] =
dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];
dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];
dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states;
}