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drm/amd/display: Add i2c speed arbitration for dc_i2c and hdcp_i2c

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[why]
HDCP 1.4 failed on SL8800 SW w/a test driver use.

[how]
Slow down the HW i2c speed when used by HW i2c.
This request: each acquired_i2c_engine setup the i2c speed needed
and sets the I2c engine for HDCP use at release_engine.

This covers SW using HW i2c engine and HDCP using HW i2c engine.
for dmcu using HW i2c engine, needs add similar logic in dmcu fw.

Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Charlene Liu
2020-09-21 14:24:09 -04:00
committed by Alex Deucher
parent 54e8094a76
commit b15cde19c3
11 changed files with 20 additions and 3 deletions
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3
drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
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@@ -970,6 +970,7 @@ static bool dce80_construct(
pool->base.timing_generator_count = res_cap.num_timing_generator;
dc->caps.max_downscale_ratio = 200;
dc->caps.i2c_speed_in_khz = 40;
dc->caps.i2c_speed_in_khz_hdcp = 40;
dc->caps.max_cursor_size = 128;
dc->caps.dual_link_dvi = true;
dc->caps.extended_aux_timeout_support = false;
@@ -1168,6 +1169,7 @@ static bool dce81_construct(
pool->base.timing_generator_count = res_cap_81.num_timing_generator;
dc->caps.max_downscale_ratio = 200;
dc->caps.i2c_speed_in_khz = 40;
dc->caps.i2c_speed_in_khz_hdcp = 40;
dc->caps.max_cursor_size = 128;
dc->caps.is_apu = true;
@@ -1365,6 +1367,7 @@ static bool dce83_construct(
pool->base.timing_generator_count = res_cap_83.num_timing_generator;
dc->caps.max_downscale_ratio = 200;
dc->caps.i2c_speed_in_khz = 40;
dc->caps.i2c_speed_in_khz_hdcp = 40;
dc->caps.max_cursor_size = 128;
dc->caps.is_apu = true;