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KVM: selftests: Consolidate KVM_{G,S}ET_ONE_REG helpers

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Rework vcpu_{g,s}et_reg() to provide the APIs that tests actually want to
use, and drop the three "one-off" implementations that cropped up due to
the poor API.

Ignore the handful of direct KVM_{G,S}ET_ONE_REG calls that don't fit the
APIs for one reason or another.

No functional change intended.

Signed-off-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Sean Christopherson
2022-06-01 17:16:11 -07:00
committed by Paolo Bonzini
parent 45f568084a
commit bfff0f60db
10 changed files with 94 additions and 133 deletions
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84
tools/testing/selftests/kvm/lib/riscv/processor.c
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@@ -198,46 +198,46 @@ void riscv_vcpu_mmu_setup(struct kvm_vm *vm, int vcpuid)
satp = (vm->pgd >> PGTBL_PAGE_SIZE_SHIFT) & SATP_PPN;
satp |= SATP_MODE_48;
set_reg(vm, vcpuid, RISCV_CSR_REG(satp), satp);
vcpu_set_reg(vm, vcpuid, RISCV_CSR_REG(satp), satp);
}
void vcpu_arch_dump(FILE *stream, struct kvm_vm *vm, uint32_t vcpuid, uint8_t indent)
{
struct kvm_riscv_core core;
get_reg(vm, vcpuid, RISCV_CORE_REG(mode), &core.mode);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.pc), &core.regs.pc);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.ra), &core.regs.ra);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.sp), &core.regs.sp);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.gp), &core.regs.gp);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.tp), &core.regs.tp);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t0), &core.regs.t0);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t1), &core.regs.t1);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t2), &core.regs.t2);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s0), &core.regs.s0);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s1), &core.regs.s1);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a0), &core.regs.a0);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a1), &core.regs.a1);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a2), &core.regs.a2);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a3), &core.regs.a3);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a4), &core.regs.a4);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a5), &core.regs.a5);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a6), &core.regs.a6);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a7), &core.regs.a7);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s2), &core.regs.s2);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s3), &core.regs.s3);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s4), &core.regs.s4);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s5), &core.regs.s5);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s6), &core.regs.s6);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s7), &core.regs.s7);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s8), &core.regs.s8);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s9), &core.regs.s9);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s10), &core.regs.s10);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s11), &core.regs.s11);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t3), &core.regs.t3);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t4), &core.regs.t4);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t5), &core.regs.t5);
get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t6), &core.regs.t6);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(mode), &core.mode);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.pc), &core.regs.pc);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.ra), &core.regs.ra);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.sp), &core.regs.sp);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.gp), &core.regs.gp);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.tp), &core.regs.tp);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t0), &core.regs.t0);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t1), &core.regs.t1);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t2), &core.regs.t2);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s0), &core.regs.s0);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s1), &core.regs.s1);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a0), &core.regs.a0);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a1), &core.regs.a1);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a2), &core.regs.a2);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a3), &core.regs.a3);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a4), &core.regs.a4);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a5), &core.regs.a5);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a6), &core.regs.a6);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.a7), &core.regs.a7);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s2), &core.regs.s2);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s3), &core.regs.s3);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s4), &core.regs.s4);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s5), &core.regs.s5);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s6), &core.regs.s6);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s7), &core.regs.s7);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s8), &core.regs.s8);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s9), &core.regs.s9);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s10), &core.regs.s10);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.s11), &core.regs.s11);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t3), &core.regs.t3);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t4), &core.regs.t4);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t5), &core.regs.t5);
vcpu_get_reg(vm, vcpuid, RISCV_CORE_REG(regs.t6), &core.regs.t6);
fprintf(stream,
" MODE: 0x%lx\n", core.mode);
@@ -302,17 +302,17 @@ struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id,
/* Setup global pointer of guest to be same as the host */
asm volatile (
"add %0, gp, zero" : "=r" (current_gp) : : "memory");
set_reg(vm, vcpu_id, RISCV_CORE_REG(regs.gp), current_gp);
vcpu_set_reg(vm, vcpu_id, RISCV_CORE_REG(regs.gp), current_gp);
/* Setup stack pointer and program counter of guest */
set_reg(vm, vcpu_id, RISCV_CORE_REG(regs.sp),
stack_vaddr + stack_size);
set_reg(vm, vcpu_id, RISCV_CORE_REG(regs.pc),
(unsigned long)guest_code);
vcpu_set_reg(vm, vcpu_id, RISCV_CORE_REG(regs.sp),
stack_vaddr + stack_size);
vcpu_set_reg(vm, vcpu_id, RISCV_CORE_REG(regs.pc),
(unsigned long)guest_code);
/* Setup default exception vector of guest */
set_reg(vm, vcpu_id, RISCV_CSR_REG(stvec),
(unsigned long)guest_unexp_trap);
vcpu_set_reg(vm, vcpu_id, RISCV_CSR_REG(stvec),
(unsigned long)guest_unexp_trap);
return vcpu;
}
@@ -355,7 +355,7 @@ void vcpu_args_set(struct kvm_vm *vm, uint32_t vcpuid, unsigned int num, ...)
id = RISCV_CORE_REG(regs.a7);
break;
}
set_reg(vm, vcpuid, id, va_arg(ap, uint64_t));
vcpu_set_reg(vm, vcpuid, id, va_arg(ap, uint64_t));
}
va_end(ap);