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drm/amd/display: fix dcn pipe reset sequence
This change fixes dcn10 front end reset sequence. Previously we would reset front end during flip which led to issues in certain MPO and 4k/5k scenarios. We would also never properly power gate our front end. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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committed by
Alex Deucher
parent
7f524a0d83
commit
cfe4645e17
@@ -2380,7 +2380,7 @@ static void amdgpu_dm_do_flip(
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surface_updates->flip_addr = &addr;
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dc_update_surfaces_for_stream(adev->dm.dc, surface_updates, 1, acrtc->stream);
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dc_update_surfaces_and_stream(adev->dm.dc, surface_updates, 1, acrtc->stream, NULL);
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DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
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__func__,
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