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drm/amd/display: update sr_exit latency for z8

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This is based on real asic performance result.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Charlene Liu
2024-09-25 20:57:00 -04:00
committed by Alex Deucher
parent 10ce17b7fb
commit de08e41930
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
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@@ -204,8 +204,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_51_soc = {
.num_states = 8,
.sr_exit_time_us = 28.0,
.sr_enter_plus_exit_time_us = 30.0,
.sr_exit_z8_time_us = 250.0,
.sr_enter_plus_exit_z8_time_us = 350.0,
.sr_exit_z8_time_us = 263.0,
.sr_enter_plus_exit_z8_time_us = 363.0,
.fclk_change_latency_us = 24.0,
.usr_retraining_latency_us = 2,
.writeback_latency_us = 12.0,