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drm/i915: expand on the kernel-doc for cache_dirty

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Add some details around non-LLC platforms and cflushing, when dealing
with the flush-on-acquire, which is potentially security sensitive.

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211018174508.2137279-7-matthew.auld@intel.com
This commit is contained in:
Matthew Auld
2021-10-18 18:45:06 +01:00
parent d70af57944
commit df94fd05e6
2 changed files with 38 additions and 0 deletions
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11
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
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@@ -1922,6 +1922,17 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb)
* !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)
* but gcc's optimiser doesn't handle that as well and emits
* two jumps instead of one. Maybe one day...
*
* FIXME: There is also sync flushing in set_pages(), which
* serves a different purpose(some of the time at least).
*
* We should consider:
*
* 1. Rip out the async flush code.
*
* 2. Or make the sync flushing use the async clflush path
* using mandatory fences underneath. Currently the below
* async flush happens after we bind the object.
*/
if (unlikely(obj->cache_dirty & ~obj->cache_coherent)) {
if (i915_gem_clflush_object(obj, 0))