mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git
synced 2026-04-23 05:56:14 -04:00
drm/i915/guc: Connect UAPI to GuC multi-lrc interface
Introduce 'set parallel submit' extension to connect UAPI to GuC multi-lrc interface. Kernel doc in new uAPI should explain it all. IGT: https://patchwork.freedesktop.org/patch/447008/?series=93071&rev=1 media UMD: https://github.com/intel/media-driver/pull/1252 v2: (Daniel Vetter) - Add IGT link and placeholder for media UMD link v3: (Kernel test robot) - Fix warning in unpin engines call (John Harrison) - Reword a bunch of the kernel doc v4: (John Harrison) - Add comment why perma-pin is done after setting gem context - Update some comments / docs for proto contexts v5: (John Harrison) - Rework perma-pin comment - Add BUG_IN if context is pinned when setting gem context Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: John Harrison <John.C.Harrison@Intel.com> Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211014172005.27155-17-matthew.brost@intel.com
This commit is contained in:
Matthew Brost
committed by
John Harrison
John Harrison
parent
d38a929449
commit
e5e32171a2
@@ -556,9 +556,150 @@ set_proto_ctx_engines_bond(struct i915_user_extension __user *base, void *data)
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return 0;
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}
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static int
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set_proto_ctx_engines_parallel_submit(struct i915_user_extension __user *base,
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void *data)
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{
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struct i915_context_engines_parallel_submit __user *ext =
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container_of_user(base, typeof(*ext), base);
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const struct set_proto_ctx_engines *set = data;
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struct drm_i915_private *i915 = set->i915;
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u64 flags;
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int err = 0, n, i, j;
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u16 slot, width, num_siblings;
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struct intel_engine_cs **siblings = NULL;
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intel_engine_mask_t prev_mask;
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/* Disabling for now */
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return -ENODEV;
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/* FIXME: This is NIY for execlists */
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if (!(intel_uc_uses_guc_submission(&i915->gt.uc)))
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return -ENODEV;
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if (get_user(slot, &ext->engine_index))
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return -EFAULT;
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if (get_user(width, &ext->width))
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return -EFAULT;
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if (get_user(num_siblings, &ext->num_siblings))
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return -EFAULT;
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if (slot >= set->num_engines) {
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drm_dbg(&i915->drm, "Invalid placement value, %d >= %d\n",
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slot, set->num_engines);
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return -EINVAL;
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}
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if (set->engines[slot].type != I915_GEM_ENGINE_TYPE_INVALID) {
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drm_dbg(&i915->drm,
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"Invalid placement[%d], already occupied\n", slot);
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return -EINVAL;
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}
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if (get_user(flags, &ext->flags))
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return -EFAULT;
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if (flags) {
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drm_dbg(&i915->drm, "Unknown flags 0x%02llx", flags);
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return -EINVAL;
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}
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for (n = 0; n < ARRAY_SIZE(ext->mbz64); n++) {
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err = check_user_mbz(&ext->mbz64[n]);
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if (err)
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return err;
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}
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if (width < 2) {
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drm_dbg(&i915->drm, "Width (%d) < 2\n", width);
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return -EINVAL;
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}
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if (num_siblings < 1) {
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drm_dbg(&i915->drm, "Number siblings (%d) < 1\n",
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num_siblings);
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return -EINVAL;
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}
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siblings = kmalloc_array(num_siblings * width,
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sizeof(*siblings),
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GFP_KERNEL);
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if (!siblings)
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return -ENOMEM;
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/* Create contexts / engines */
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for (i = 0; i < width; ++i) {
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intel_engine_mask_t current_mask = 0;
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struct i915_engine_class_instance prev_engine;
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for (j = 0; j < num_siblings; ++j) {
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struct i915_engine_class_instance ci;
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n = i * num_siblings + j;
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if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) {
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err = -EFAULT;
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goto out_err;
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}
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siblings[n] =
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intel_engine_lookup_user(i915, ci.engine_class,
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ci.engine_instance);
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if (!siblings[n]) {
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drm_dbg(&i915->drm,
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"Invalid sibling[%d]: { class:%d, inst:%d }\n",
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n, ci.engine_class, ci.engine_instance);
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err = -EINVAL;
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goto out_err;
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}
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if (n) {
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if (prev_engine.engine_class !=
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ci.engine_class) {
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drm_dbg(&i915->drm,
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"Mismatched class %d, %d\n",
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prev_engine.engine_class,
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ci.engine_class);
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err = -EINVAL;
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goto out_err;
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}
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}
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prev_engine = ci;
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current_mask |= siblings[n]->logical_mask;
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}
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if (i > 0) {
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if (current_mask != prev_mask << 1) {
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drm_dbg(&i915->drm,
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"Non contiguous logical mask 0x%x, 0x%x\n",
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prev_mask, current_mask);
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err = -EINVAL;
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goto out_err;
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}
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}
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prev_mask = current_mask;
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}
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set->engines[slot].type = I915_GEM_ENGINE_TYPE_PARALLEL;
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set->engines[slot].num_siblings = num_siblings;
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set->engines[slot].width = width;
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set->engines[slot].siblings = siblings;
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return 0;
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out_err:
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kfree(siblings);
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return err;
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}
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static const i915_user_extension_fn set_proto_ctx_engines_extensions[] = {
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[I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE] = set_proto_ctx_engines_balance,
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[I915_CONTEXT_ENGINES_EXT_BOND] = set_proto_ctx_engines_bond,
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[I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT] =
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set_proto_ctx_engines_parallel_submit,
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};
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static int set_proto_ctx_engines(struct drm_i915_file_private *fpriv,
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@@ -794,6 +935,7 @@ static int intel_context_set_gem(struct intel_context *ce,
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GEM_BUG_ON(rcu_access_pointer(ce->gem_context));
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RCU_INIT_POINTER(ce->gem_context, ctx);
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GEM_BUG_ON(intel_context_is_pinned(ce));
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ce->ring_size = SZ_16K;
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i915_vm_put(ce->vm);
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@@ -818,6 +960,25 @@ static int intel_context_set_gem(struct intel_context *ce,
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return ret;
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}
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static void __unpin_engines(struct i915_gem_engines *e, unsigned int count)
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{
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while (count--) {
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struct intel_context *ce = e->engines[count], *child;
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if (!ce || !test_bit(CONTEXT_PERMA_PIN, &ce->flags))
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continue;
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for_each_child(ce, child)
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intel_context_unpin(child);
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intel_context_unpin(ce);
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}
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}
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static void unpin_engines(struct i915_gem_engines *e)
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{
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__unpin_engines(e, e->num_engines);
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}
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static void __free_engines(struct i915_gem_engines *e, unsigned int count)
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{
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while (count--) {
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@@ -933,6 +1094,40 @@ free_engines:
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return err;
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}
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static int perma_pin_contexts(struct intel_context *ce)
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{
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struct intel_context *child;
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int i = 0, j = 0, ret;
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GEM_BUG_ON(!intel_context_is_parent(ce));
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ret = intel_context_pin(ce);
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if (unlikely(ret))
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return ret;
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for_each_child(ce, child) {
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ret = intel_context_pin(child);
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if (unlikely(ret))
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goto unwind;
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++i;
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}
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set_bit(CONTEXT_PERMA_PIN, &ce->flags);
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return 0;
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unwind:
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intel_context_unpin(ce);
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for_each_child(ce, child) {
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if (j++ < i)
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intel_context_unpin(child);
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else
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break;
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}
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return ret;
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}
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static struct i915_gem_engines *user_engines(struct i915_gem_context *ctx,
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unsigned int num_engines,
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struct i915_gem_proto_engine *pe)
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@@ -946,7 +1141,7 @@ static struct i915_gem_engines *user_engines(struct i915_gem_context *ctx,
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e->num_engines = num_engines;
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for (n = 0; n < num_engines; n++) {
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struct intel_context *ce;
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struct intel_context *ce, *child;
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int ret;
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switch (pe[n].type) {
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@@ -956,7 +1151,13 @@ static struct i915_gem_engines *user_engines(struct i915_gem_context *ctx,
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case I915_GEM_ENGINE_TYPE_BALANCED:
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ce = intel_engine_create_virtual(pe[n].siblings,
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pe[n].num_siblings);
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pe[n].num_siblings, 0);
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break;
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case I915_GEM_ENGINE_TYPE_PARALLEL:
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ce = intel_engine_create_parallel(pe[n].siblings,
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pe[n].num_siblings,
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pe[n].width);
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break;
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case I915_GEM_ENGINE_TYPE_INVALID:
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@@ -977,6 +1178,30 @@ static struct i915_gem_engines *user_engines(struct i915_gem_context *ctx,
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err = ERR_PTR(ret);
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goto free_engines;
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}
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for_each_child(ce, child) {
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ret = intel_context_set_gem(child, ctx, pe->sseu);
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if (ret) {
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err = ERR_PTR(ret);
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goto free_engines;
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}
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}
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/*
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* XXX: Must be done after calling intel_context_set_gem as that
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* function changes the ring size. The ring is allocated when
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* the context is pinned. If the ring size is changed after
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* allocation we have a mismatch of the ring size and will cause
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* the context to hang. Presumably with a bit of reordering we
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* could move the perma-pin step to the backend function
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* intel_engine_create_parallel.
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*/
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if (pe[n].type == I915_GEM_ENGINE_TYPE_PARALLEL) {
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ret = perma_pin_contexts(ce);
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if (ret) {
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err = ERR_PTR(ret);
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goto free_engines;
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}
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}
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}
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return e;
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@@ -1219,6 +1444,7 @@ static void context_close(struct i915_gem_context *ctx)
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/* Flush any concurrent set_engines() */
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mutex_lock(&ctx->engines_mutex);
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unpin_engines(__context_engines_static(ctx));
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engines_idle_release(ctx, rcu_replace_pointer(ctx->engines, NULL, 1));
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i915_gem_context_set_closed(ctx);
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mutex_unlock(&ctx->engines_mutex);
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