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drm/i915/guc: Connect UAPI to GuC multi-lrc interface
Introduce 'set parallel submit' extension to connect UAPI to GuC multi-lrc interface. Kernel doc in new uAPI should explain it all. IGT: https://patchwork.freedesktop.org/patch/447008/?series=93071&rev=1 media UMD: https://github.com/intel/media-driver/pull/1252 v2: (Daniel Vetter) - Add IGT link and placeholder for media UMD link v3: (Kernel test robot) - Fix warning in unpin engines call (John Harrison) - Reword a bunch of the kernel doc v4: (John Harrison) - Add comment why perma-pin is done after setting gem context - Update some comments / docs for proto contexts v5: (John Harrison) - Rework perma-pin comment - Add BUG_IN if context is pinned when setting gem context Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: John Harrison <John.C.Harrison@Intel.com> Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211014172005.27155-17-matthew.brost@intel.com
This commit is contained in:
Matthew Brost
committed by
John Harrison
John Harrison
parent
d38a929449
commit
e5e32171a2
@@ -1824,6 +1824,7 @@ struct drm_i915_gem_context_param {
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* Extensions:
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* i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
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* i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
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* i915_context_engines_parallel_submit (I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT)
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*/
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#define I915_CONTEXT_PARAM_ENGINES 0xa
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@@ -2098,6 +2099,135 @@ struct i915_context_engines_bond {
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struct i915_engine_class_instance engines[N__]; \
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} __attribute__((packed)) name__
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/**
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* struct i915_context_engines_parallel_submit - Configure engine for
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* parallel submission.
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*
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* Setup a slot in the context engine map to allow multiple BBs to be submitted
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* in a single execbuf IOCTL. Those BBs will then be scheduled to run on the GPU
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* in parallel. Multiple hardware contexts are created internally in the i915 to
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* run these BBs. Once a slot is configured for N BBs only N BBs can be
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* submitted in each execbuf IOCTL and this is implicit behavior e.g. The user
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* doesn't tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how
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* many BBs there are based on the slot's configuration. The N BBs are the last
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* N buffer objects or first N if I915_EXEC_BATCH_FIRST is set.
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*
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* The default placement behavior is to create implicit bonds between each
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* context if each context maps to more than 1 physical engine (e.g. context is
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* a virtual engine). Also we only allow contexts of same engine class and these
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* contexts must be in logically contiguous order. Examples of the placement
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* behavior are described below. Lastly, the default is to not allow BBs to be
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* preempted mid-batch. Rather insert coordinated preemption points on all
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* hardware contexts between each set of BBs. Flags could be added in the future
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* to change both of these default behaviors.
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*
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* Returns -EINVAL if hardware context placement configuration is invalid or if
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* the placement configuration isn't supported on the platform / submission
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* interface.
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* Returns -ENODEV if extension isn't supported on the platform / submission
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* interface.
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*
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* .. code-block:: none
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*
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* Examples syntax:
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* CS[X] = generic engine of same class, logical instance X
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* INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
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*
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* Example 1 pseudo code:
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* set_engines(INVALID)
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* set_parallel(engine_index=0, width=2, num_siblings=1,
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* engines=CS[0],CS[1])
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*
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* Results in the following valid placement:
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* CS[0], CS[1]
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*
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* Example 2 pseudo code:
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* set_engines(INVALID)
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* set_parallel(engine_index=0, width=2, num_siblings=2,
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* engines=CS[0],CS[2],CS[1],CS[3])
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*
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* Results in the following valid placements:
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* CS[0], CS[1]
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* CS[2], CS[3]
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*
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* This can be thought of as two virtual engines, each containing two
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* engines thereby making a 2D array. However, there are bonds tying the
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* entries together and placing restrictions on how they can be scheduled.
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* Specifically, the scheduler can choose only vertical columns from the 2D
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* array. That is, CS[0] is bonded to CS[1] and CS[2] to CS[3]. So if the
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* scheduler wants to submit to CS[0], it must also choose CS[1] and vice
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* versa. Same for CS[2] requires also using CS[3].
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* VE[0] = CS[0], CS[2]
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* VE[1] = CS[1], CS[3]
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*
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* Example 3 pseudo code:
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* set_engines(INVALID)
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* set_parallel(engine_index=0, width=2, num_siblings=2,
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* engines=CS[0],CS[1],CS[1],CS[3])
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*
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* Results in the following valid and invalid placements:
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* CS[0], CS[1]
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* CS[1], CS[3] - Not logically contiguous, return -EINVAL
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*/
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struct i915_context_engines_parallel_submit {
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/**
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* @base: base user extension.
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*/
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struct i915_user_extension base;
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/**
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* @engine_index: slot for parallel engine
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*/
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__u16 engine_index;
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/**
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* @width: number of contexts per parallel engine or in other words the
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* number of batches in each submission
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*/
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__u16 width;
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/**
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* @num_siblings: number of siblings per context or in other words the
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* number of possible placements for each submission
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*/
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__u16 num_siblings;
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/**
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* @mbz16: reserved for future use; must be zero
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*/
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__u16 mbz16;
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/**
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* @flags: all undefined flags must be zero, currently not defined flags
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*/
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__u64 flags;
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/**
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* @mbz64: reserved for future use; must be zero
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*/
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__u64 mbz64[3];
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/**
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* @engines: 2-d array of engine instances to configure parallel engine
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*
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* length = width (i) * num_siblings (j)
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* index = j + i * num_siblings
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*/
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struct i915_engine_class_instance engines[0];
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} __packed;
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#define I915_DEFINE_CONTEXT_ENGINES_PARALLEL_SUBMIT(name__, N__) struct { \
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struct i915_user_extension base; \
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__u16 engine_index; \
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__u16 width; \
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__u16 num_siblings; \
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__u16 mbz16; \
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__u64 flags; \
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__u64 mbz64[3]; \
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struct i915_engine_class_instance engines[N__]; \
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} __attribute__((packed)) name__
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/**
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* DOC: Context Engine Map uAPI
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*
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@@ -2157,6 +2287,7 @@ struct i915_context_param_engines {
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__u64 extensions; /* linked chain of extension blocks, 0 terminates */
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#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
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#define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */
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#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
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struct i915_engine_class_instance engines[0];
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} __attribute__((packed));
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