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iio: accel: adxl313: make use of regmap cache

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Setup regmap cache to cache register configuration, reducing bus traffic
for repeated accesses to non volatile registers.

Reviewed-by: Andy Shevchenko <andy@kernel.org>
Signed-off-by: Lothar Rubusch <l.rubusch@gmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://patch.msgid.link/20250702230819.19353-2-l.rubusch@gmail.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Lothar Rubusch
2025-07-02 23:08:12 +00:00
committed by Jonathan Cameron
parent 1a4deda6c6
commit ec489d9157
4 changed files with 33 additions and 0 deletions
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3
drivers/iio/accel/adxl313.h
View File

@@ -22,6 +22,7 @@
#define ADXL313_REG_BW_RATE 0x2C #define ADXL313_REG_BW_RATE 0x2C
#define ADXL313_REG_POWER_CTL 0x2D #define ADXL313_REG_POWER_CTL 0x2D
#define ADXL313_REG_INT_MAP 0x2F #define ADXL313_REG_INT_MAP 0x2F
#define ADXL313_REG_INT_SOURCE 0x30
#define ADXL313_REG_DATA_FORMAT 0x31 #define ADXL313_REG_DATA_FORMAT 0x31
#define ADXL313_REG_DATA_AXIS(index) (0x32 + ((index) * 2)) #define ADXL313_REG_DATA_AXIS(index) (0x32 + ((index) * 2))
#define ADXL313_REG_FIFO_CTL 0x38 #define ADXL313_REG_FIFO_CTL 0x38
@@ -54,6 +55,8 @@ extern const struct regmap_access_table adxl312_writable_regs_table;
extern const struct regmap_access_table adxl313_writable_regs_table; extern const struct regmap_access_table adxl313_writable_regs_table;
extern const struct regmap_access_table adxl314_writable_regs_table; extern const struct regmap_access_table adxl314_writable_regs_table;
bool adxl313_is_volatile_reg(struct device *dev, unsigned int reg);
enum adxl313_device_type { enum adxl313_device_type {
ADXL312, ADXL312,
ADXL313, ADXL313,

18
drivers/iio/accel/adxl313_core.c
View File

@@ -46,6 +46,24 @@ const struct regmap_access_table adxl314_readable_regs_table = {
}; };
EXPORT_SYMBOL_NS_GPL(adxl314_readable_regs_table, "IIO_ADXL313"); EXPORT_SYMBOL_NS_GPL(adxl314_readable_regs_table, "IIO_ADXL313");
bool adxl313_is_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case ADXL313_REG_DATA_AXIS(0):
case ADXL313_REG_DATA_AXIS(1):
case ADXL313_REG_DATA_AXIS(2):
case ADXL313_REG_DATA_AXIS(3):
case ADXL313_REG_DATA_AXIS(4):
case ADXL313_REG_DATA_AXIS(5):
case ADXL313_REG_FIFO_STATUS:
case ADXL313_REG_INT_SOURCE:
return true;
default:
return false;
}
}
EXPORT_SYMBOL_NS_GPL(adxl313_is_volatile_reg, "IIO_ADXL313");
static int adxl312_check_id(struct device *dev, static int adxl312_check_id(struct device *dev,
struct adxl313_data *data) struct adxl313_data *data)
{ {

6
drivers/iio/accel/adxl313_i2c.c
View File

@@ -21,6 +21,8 @@ static const struct regmap_config adxl31x_i2c_regmap_config[] = {
.rd_table = &adxl312_readable_regs_table, .rd_table = &adxl312_readable_regs_table,
.wr_table = &adxl312_writable_regs_table, .wr_table = &adxl312_writable_regs_table,
.max_register = 0x39, .max_register = 0x39,
.volatile_reg = adxl313_is_volatile_reg,
.cache_type = REGCACHE_MAPLE,
}, },
[ADXL313] = { [ADXL313] = {
.reg_bits = 8, .reg_bits = 8,
@@ -28,6 +30,8 @@ static const struct regmap_config adxl31x_i2c_regmap_config[] = {
.rd_table = &adxl313_readable_regs_table, .rd_table = &adxl313_readable_regs_table,
.wr_table = &adxl313_writable_regs_table, .wr_table = &adxl313_writable_regs_table,
.max_register = 0x39, .max_register = 0x39,
.volatile_reg = adxl313_is_volatile_reg,
.cache_type = REGCACHE_MAPLE,
}, },
[ADXL314] = { [ADXL314] = {
.reg_bits = 8, .reg_bits = 8,
@@ -35,6 +39,8 @@ static const struct regmap_config adxl31x_i2c_regmap_config[] = {
.rd_table = &adxl314_readable_regs_table, .rd_table = &adxl314_readable_regs_table,
.wr_table = &adxl314_writable_regs_table, .wr_table = &adxl314_writable_regs_table,
.max_register = 0x39, .max_register = 0x39,
.volatile_reg = adxl313_is_volatile_reg,
.cache_type = REGCACHE_MAPLE,
}, },
}; };

6
drivers/iio/accel/adxl313_spi.c
View File

@@ -24,6 +24,8 @@ static const struct regmap_config adxl31x_spi_regmap_config[] = {
.max_register = 0x39, .max_register = 0x39,
/* Setting bits 7 and 6 enables multiple-byte read */ /* Setting bits 7 and 6 enables multiple-byte read */
.read_flag_mask = BIT(7) | BIT(6), .read_flag_mask = BIT(7) | BIT(6),
.volatile_reg = adxl313_is_volatile_reg,
.cache_type = REGCACHE_MAPLE,
}, },
[ADXL313] = { [ADXL313] = {
.reg_bits = 8, .reg_bits = 8,
@@ -33,6 +35,8 @@ static const struct regmap_config adxl31x_spi_regmap_config[] = {
.max_register = 0x39, .max_register = 0x39,
/* Setting bits 7 and 6 enables multiple-byte read */ /* Setting bits 7 and 6 enables multiple-byte read */
.read_flag_mask = BIT(7) | BIT(6), .read_flag_mask = BIT(7) | BIT(6),
.volatile_reg = adxl313_is_volatile_reg,
.cache_type = REGCACHE_MAPLE,
}, },
[ADXL314] = { [ADXL314] = {
.reg_bits = 8, .reg_bits = 8,
@@ -42,6 +46,8 @@ static const struct regmap_config adxl31x_spi_regmap_config[] = {
.max_register = 0x39, .max_register = 0x39,
/* Setting bits 7 and 6 enables multiple-byte read */ /* Setting bits 7 and 6 enables multiple-byte read */
.read_flag_mask = BIT(7) | BIT(6), .read_flag_mask = BIT(7) | BIT(6),
.volatile_reg = adxl313_is_volatile_reg,
.cache_type = REGCACHE_MAPLE,
}, },
}; };