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cxl: docs/linux/cxl-driver - add example configurations
Add 4 example configurations: - single device - cross-host-bridge interleave - intra-host-bridge-interleave - multi-level interleave Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-11-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
This commit is contained in:
Gregory Price
committed by
Dave Jiang
Dave Jiang
parent
2e2865a1d0
commit
ef3a43a691
@@ -0,0 +1,246 @@
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.. SPDX-License-Identifier: GPL-2.0
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=============
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Single Device
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=============
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This cxl-cli configuration dump shows the following host configuration:
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* A single socket system with one CXL root
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* CXL Root has Four (4) CXL Host Bridges
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* One CXL Host Bridges has a single CXL Memory Expander Attached
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* No interleave is present.
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This output is generated by :code:`cxl list -v` and describes the relationships
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between objects exposed in :code:`/sys/bus/cxl/devices/`.
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::
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[
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{
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"bus":"root0",
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"provider":"ACPI.CXL",
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"nr_dports":4,
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"dports":[
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{
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"dport":"pci0000:00",
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"alias":"ACPI0016:01",
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"id":0
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},
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{
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"dport":"pci0000:a8",
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"alias":"ACPI0016:02",
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"id":4
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},
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{
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"dport":"pci0000:2a",
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"alias":"ACPI0016:03",
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"id":1
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},
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{
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"dport":"pci0000:d2",
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"alias":"ACPI0016:00",
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"id":5
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}
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],
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This chunk shows the CXL "bus" (root0) has 4 downstream ports attached to CXL
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Host Bridges. The `Root` can be considered the singular upstream port attached
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to the platform's memory controller - which routes memory requests to it.
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The `ports:root0` section lays out how each of these downstream ports are
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configured. If a port is not configured (id's 0, 1, and 4), they are omitted.
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::
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"ports:root0":[
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{
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"port":"port1",
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"host":"pci0000:d2",
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"depth":1,
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"nr_dports":3,
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"dports":[
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{
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"dport":"0000:d2:01.1",
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"alias":"device:02",
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"id":0
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},
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{
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"dport":"0000:d2:01.3",
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"alias":"device:05",
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"id":2
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},
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{
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"dport":"0000:d2:07.1",
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"alias":"device:0d",
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"id":113
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}
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],
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This chunk shows the available downstream ports associated with the CXL Host
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Bridge :code:`port1`. In this case, :code:`port1` has 3 available downstream
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ports: :code:`dport1`, :code:`dport2`, and :code:`dport113`..
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::
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"endpoints:port1":[
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{
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"endpoint":"endpoint5",
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"host":"mem0",
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"parent_dport":"0000:d2:01.1",
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"depth":2,
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"memdev":{
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"memdev":"mem0",
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"ram_size":137438953472,
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"serial":0,
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"numa_node":0,
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"host":"0000:d3:00.0"
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},
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"decoders:endpoint5":[
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{
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"decoder":"decoder5.0",
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"resource":825975898112,
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"size":137438953472,
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"interleave_ways":1,
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"region":"region0",
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"dpa_resource":0,
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"dpa_size":137438953472,
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"mode":"ram"
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}
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]
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}
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],
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This chunk shows the endpoints attached to the host bridge :code:`port1`.
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:code:`endpoint5` contains a single configured decoder :code:`decoder5.0`
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which has the same interleave configuration as :code:`region0` (shown later).
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Next we have the decoders belonging to the host bridge:
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::
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"decoders:port1":[
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{
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"decoder":"decoder1.0",
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"resource":825975898112,
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"size":137438953472,
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"interleave_ways":1,
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"region":"region0",
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"nr_targets":1,
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"targets":[
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{
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"target":"0000:d2:01.1",
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"alias":"device:02",
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"position":0,
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"id":0
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}
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]
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}
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]
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},
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Host Bridge :code:`port1` has a single decoder (:code:`decoder1.0`), whose only
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target is :code:`dport1` - which is attached to :code:`endpoint5`.
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The next chunk shows the three CXL host bridges without attached endpoints.
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::
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{
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"port":"port2",
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"host":"pci0000:00",
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"depth":1,
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"nr_dports":2,
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"dports":[
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{
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"dport":"0000:00:01.3",
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"alias":"device:55",
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"id":2
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},
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{
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"dport":"0000:00:07.1",
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"alias":"device:5d",
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"id":113
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}
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]
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},
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{
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"port":"port3",
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"host":"pci0000:a8",
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"depth":1,
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"nr_dports":1,
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"dports":[
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{
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"dport":"0000:a8:01.1",
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"alias":"device:c3",
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"id":0
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}
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]
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},
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{
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"port":"port4",
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"host":"pci0000:2a",
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"depth":1,
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"nr_dports":1,
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"dports":[
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{
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"dport":"0000:2a:01.1",
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"alias":"device:d0",
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"id":0
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}
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]
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}
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],
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Next we have the `Root Decoders` belonging to :code:`root0`. This root decoder
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is a pass-through decoder because :code:`interleave_ways` is set to :code:`1`.
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This information is generated by the CXL driver reading the ACPI CEDT CMFWS.
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::
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"decoders:root0":[
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{
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"decoder":"decoder0.0",
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"resource":825975898112,
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"size":137438953472,
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"interleave_ways":1,
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"max_available_extent":0,
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"volatile_capable":true,
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"nr_targets":1,
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"targets":[
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{
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"target":"pci0000:d2",
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"alias":"ACPI0016:00",
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"position":0,
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"id":5
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}
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],
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Finally we have the `Memory Region` associated with the `Root Decoder`
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:code:`decoder0.0`. This region describes the discrete region associated
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with the lone device.
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::
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"regions:decoder0.0":[
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{
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"region":"region0",
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"resource":825975898112,
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"size":137438953472,
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"type":"ram",
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"interleave_ways":1,
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"decode_state":"commit",
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"mappings":[
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{
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"position":0,
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"memdev":"mem0",
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"decoder":"decoder5.0"
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}
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]
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}
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]
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}
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]
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}
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]
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