drm/amdgpu: add amdgpu_jpeg_sched_mask debugfs

JPEG_4_0_3 has up to 32 jpeg cores and a single mjpeg video decode
will use all available cores on the hardware. This debugfs entry
helps to disable or enable job submission to a cluster of cores or
one specific core in the ip for debugging. The entry is populated
only if there is at least two or more cores in the jpeg ip.

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Sathishkumar S
2024-09-09 14:52:39 +05:30
committed by Alex Deucher
parent 8b1f72876b
commit f0b19b84d3
3 changed files with 76 additions and 0 deletions

View File

@@ -342,3 +342,76 @@ int amdgpu_jpeg_psp_update_sram(struct amdgpu_device *adev, int inst_idx,
return psp_execute_ip_fw_load(&adev->psp, &ucode);
}
/*
* debugfs for to enable/disable jpeg job submission to specific core.
*/
#if defined(CONFIG_DEBUG_FS)
static int amdgpu_debugfs_jpeg_sched_mask_set(void *data, u64 val)
{
struct amdgpu_device *adev = (struct amdgpu_device *)data;
u32 i, j;
u64 mask = 0;
struct amdgpu_ring *ring;
if (!adev)
return -ENODEV;
mask = (1 << (adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings)) - 1;
if ((val & mask) == 0)
return -EINVAL;
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
ring = &adev->jpeg.inst[i].ring_dec[j];
if (val & (1 << ((i * adev->jpeg.num_jpeg_rings) + j)))
ring->sched.ready = true;
else
ring->sched.ready = false;
}
}
/* publish sched.ready flag update effective immediately across smp */
smp_rmb();
return 0;
}
static int amdgpu_debugfs_jpeg_sched_mask_get(void *data, u64 *val)
{
struct amdgpu_device *adev = (struct amdgpu_device *)data;
u32 i, j;
u64 mask = 0;
struct amdgpu_ring *ring;
if (!adev)
return -ENODEV;
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
ring = &adev->jpeg.inst[i].ring_dec[j];
if (ring->sched.ready)
mask |= 1 << ((i * adev->jpeg.num_jpeg_rings) + j);
}
}
*val = mask;
return 0;
}
DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_jpeg_sched_mask_fops,
amdgpu_debugfs_jpeg_sched_mask_get,
amdgpu_debugfs_jpeg_sched_mask_set, "%llx\n");
#endif
void amdgpu_debugfs_jpeg_sched_mask_init(struct amdgpu_device *adev)
{
#if defined(CONFIG_DEBUG_FS)
struct drm_minor *minor = adev_to_drm(adev)->primary;
struct dentry *root = minor->debugfs_root;
char name[32];
if (!(adev->jpeg.num_jpeg_inst > 1) && !(adev->jpeg.num_jpeg_rings > 1))
return;
sprintf(name, "amdgpu_jpeg_sched_mask");
debugfs_create_file(name, 0600, root, adev,
&amdgpu_debugfs_jpeg_sched_mask_fops);
#endif
}