Merge tag 'tag-chrome-platform-for-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/chrome-platform/linux

Pull chrome platform updates from Tzung-Bi Shih:
 "cros_ec:
   - Fix wrong error handling path
   - Clean-up patches

  cros_ec_chardev:
   - Re-introduce cros_ec_cmd_xfer to fix ABI broken

  cros_ec_lpcs:
   - Support the Framework Laptop

  cros_ec_typec:
   - Fix NULL dereference

  chromeos_acpi:
   - Add ChromeOS ACPI device driver
   - Fix Sphinx errors when `make htmldocs`

  misc:
   - Drop BUG_ON()s"

* tag 'tag-chrome-platform-for-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/chrome-platform/linux:
  platform/chrome: Use imperative mood for ChromeOS ACPI sysfs ABI descriptions
  platform/chrome: Use tables for values lists of ChromeOS ACPI sysfs ABI
  platform/chrome: cros_ec_spi: drop BUG_ON() if `din` isn't large enough
  platform/chrome: cros_ec_spi: drop unneeded BUG_ON()
  platform/chrome: cros_ec_i2c: drop BUG_ON() in cros_ec_pkt_xfer_i2c()
  platform/chrome: cros_ec_proto: drop BUG_ON() in cros_ec_get_host_event()
  platform/chrome: cros_ec_proto: drop BUG_ON() in cros_ec_prepare_tx()
  platform/chrome: correct cros_ec_prepare_tx() usage
  platform/chrome: cros_ec_proto: drop unneeded BUG_ON() in prepare_packet()
  platform/chrome: Add ChromeOS ACPI device driver
  platform/chrome: cros_ec_typec: Check for EC driver
  platform/chrome: cros_ec_lpcs: reserve the MEC LPC I/O ports first
  platform/chrome: cros_ec_lpcs: detect the Framework Laptop
  platform/chrome: Re-introduce cros_ec_cmd_xfer and use it for ioctls
  platform/chrome: cros_ec: append newline to all logs
  platform/chrome: cros_ec: sort header inclusion alphabetically
  platform/chrome: cros_ec: determine `wake_enabled` in cros_ec_suspend()
  platform/chrome: cros_ec: remove unused variable `was_wake_device`
  platform/chrome: cros_ec: fix error handling in cros_ec_register()

include/linux/platform_data/cros_ec_commands.h

@@ -51,10 +51,14 @@
 /*
  * The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff
  * and they tell the kernel that so we have to think of it as two parts.
+ *
+ * Other BIOSes report only the I/O port region spanned by the Microchip
+ * MEC series EC; an attempt to address a larger region may fail.
  */
-#define EC_HOST_CMD_REGION0    0x800
-#define EC_HOST_CMD_REGION1    0x880
-#define EC_HOST_CMD_REGION_SIZE 0x80
+#define EC_HOST_CMD_REGION0       0x800
+#define EC_HOST_CMD_REGION1       0x880
+#define EC_HOST_CMD_REGION_SIZE    0x80
+#define EC_HOST_CMD_MEC_REGION_SIZE 0x8
 
 /* EC command register bit functions */
 #define EC_LPC_CMDR_DATA	BIT(0)  /* Data ready for host to read */

include/linux/platform_data/cros_ec_proto.h

@@ -76,8 +76,6 @@ struct cros_ec_command {
  * struct cros_ec_device - Information about a ChromeOS EC device.
  * @phys_name: Name of physical comms layer (e.g. 'i2c-4').
  * @dev: Device pointer for physical comms device
- * @was_wake_device: True if this device was set to wake the system from
- *                   sleep at the last suspend.
  * @cros_class: The class structure for this device.
  * @cmd_readmem: Direct read of the EC memory-mapped region, if supported.
  *     @offset: Is within EC_LPC_ADDR_MEMMAP region.
@@ -137,7 +135,6 @@ struct cros_ec_device {
 	/* These are used by other drivers that want to talk to the EC */
 	const char *phys_name;
 	struct device *dev;
-	bool was_wake_device;
 	struct class *cros_class;
 	int (*cmd_readmem)(struct cros_ec_device *ec, unsigned int offset,
 			   unsigned int bytes, void *dest);
@@ -216,6 +213,9 @@ int cros_ec_prepare_tx(struct cros_ec_device *ec_dev,
 int cros_ec_check_result(struct cros_ec_device *ec_dev,
 			 struct cros_ec_command *msg);
 
+int cros_ec_cmd_xfer(struct cros_ec_device *ec_dev,
+		     struct cros_ec_command *msg);
+
 int cros_ec_cmd_xfer_status(struct cros_ec_device *ec_dev,
 			    struct cros_ec_command *msg);